LOGIC DIAGRAM

TTL Outputs

TTL/ECL Clock Inputs

TTL Control Inputs

VBB

DE

DT

SEL

R

DE

MUX

÷ 2

÷ 4

Q0

Q1

Q2

Q3

Q0

Q1

Q4

Q5

MC10H640 MC100H640

MOTOROLA

MECL Data

DL122 — Rev 6

2–2

PIN NAMES

PIN

FUNCTION

GT

VT

VE

GE

DE, DE

VBB

DT

Qn, Qn

SEL

R

TTL Ground (0 V)

TTL VCC (+5.0 V)

ECL VCC (+5.0 V)

ECL Ground (0 V)

ECL Signal Input (positive ECL)

VBB Reference Output

TTL Signal Input

Signal Outputs (TTL)

Input Select (TTL)

Reset (TTL)

AC CHARACTERISTICS (VT = VE = 5.0V

±5%)

0

°C

25

°C

85

°C

Symbol

Characteristic

Min

Max

Min

Max

Min

Max

Unit

Condition

tPLH

Propagation Delay ECL

D to Output

Q0–Q3

4.9

5.9

4.9

5.9

5.2

6.2

ns

CL = 25pF

tPLH

Propagation Delay TTL

D to Output

5.0

6.0

5.0

6.0

5.3

6.3

ns

CL = 25pF

tskwd*

Within–Device Skew

0.5

0.5

0.5

ns

CL = 25pF

tPLH

Propagation Delay ECL

D to Output

Q0, Q1

4.9

5.9

4.9

5.9

5.2

6.2

ns

CL = 25pF

tPLH

Propagation Delay TTL

D to Output

5.0

6.0

5.0

6.0

5.3

6.3

ns

CL = 25pF

tPLH

Propagation Delay ECL

D to Output

Q4, Q5

4.9

5.9

4.9

5.9

5.2

6.2

ns

CL = 25pF

tPLH

Propagation Delay TTL

D to Output

5.0

6.0

5.0

6.0

5.3

6.3

ns

CL = 25pF

tPD

Propagation Delay

R to Output

All

Outputs

4.3

6.3

4.3

6.3

5.0

7.0

ns

CL = 25pF

tR

tF

Output Rise/Fall Time

0.8 V – 2.0 V

All

Outputs

2.5

2.5

2.5

2.5

2.5

2.5

ns

CL = 25pF

fmax

Maximum Input Frequency

135

135

135

MHz

CL = 25pF

tpw

Minimum Pulse Width

1.50

1.50

1.50

ns

trr

Reset Recovery Time

1.25

1.25

1.25

ns

* Within–Device Skew defined as identical transitions on similar paths through a device.