EDS2732CABH-1AL-E datasheet(7/48 Pages) ELPIDA

Part #	EDS2732CABH-1AL-E

Description	256M bits SDRAM (8M words x 32 bits)

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Manufacturer	ELPIDA [Elpida Memory]

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EDS2732CABH

Data Sheet E0397E40 (Ver. 4.0)

7

AC Characteristics (TA = 0 to +70

°°°°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)

-75

-1A

Parameter

Symbol

min.

max.

min.

max.

Unit

Notes

System clock cycle time

(CL = 2)

tCK

10

—

10

—

ns

1

(CL = 3)

tCK

7.5

—

10

—

ns

1

CLK high pulse width

tCH

2.5

—

3

—

ns

1

CLK low pulse width

tCL

2.5

—

3

—

ns

1

Access time from CLK

tAC

—

5.4

—

6

ns

1, 2

Data-out hold time

tOH

2.0

—

2.0

—

ns

1, 2

CLK to Data-out low impedance

tLZ

0

—

0

—

ns

1, 2, 3

CLK to Data-out high impedance tHZ

—

5.4

—

6

ns

1, 4

Input setup time

tSI

1.5

—

2

—

ns

1

Input hold time

tHI

0.8

—

1

—

ns

1

Ref/Active to Ref/Active

command period

tRC

67.5

—

70

—

ns

1

Active to Precharge command

period

tRAS

45

120000

50

120000

ns

1

Active command to column

command (same bank)

tRCD

20

—

20

—

ns

1

Precharge to active command

period

tRP

20

—

20

—

ns

1

Write recovery or data-in to

precharge lead time

tDPL

15

—

20

—

ns

1

Last data into active latency

tDAL

2CLK + 20ns —

Active (a) to Active (b) command

period

tRRD

15

—

20

—

ns

1

Transition time (rise and fall)

tT

0.5

5

0.5

5

ns

Refresh period

(4096 refresh cycles)

tREF

—

64

—

64

ms

Notes: 1. AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 1.2V.

2. Access time is measured at 1.2V. Load condition is CL = 30pF.

3. tLZ (min.) defines the time at which the outputs achieves the low impedance state.

4. tHZ (max.) defines the time at which the outputs achieves the high impedance state.

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