EDS2532EEBH-9A datasheet(5/50 Pages) ELPIDA

Part #	EDS2532EEBH-9A

Description	256M bits SDRAM (8M words x 32 bits)

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Manufacturer	ELPIDA [Elpida Memory]

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EDS2532EEBH-9A

Preliminary Data Sheet E0617E40 (Ver. 4.0)

5

DC Characteristics 1 (TA = 0

°C to +70°C, VDD, VDDQ = 1.8V ± 0.1V, VSS, VSSQ = 0V)

Parameter

/CAS latency

Symbol

Grade

max.

Unit

Test condition

Notes

Operating current

IDD1

75

mA

Burst length = 1

tRC = tRC (min.)

VIL ≤ 0.3V, VIH ≥ 0.8V

× VDD

1, 2, 3

Standby current in power down

IDD2P

3

mA

CKE ≤ 0.3V,

tCK = tCK (min.)

VIL ≤ 0.3V, VIH ≥ 0.8V

× VDD

6

Standby current in power down

(input signal stable)

IDD2PS

2

mA

CKE ≤ 0.3V, tCK =

∞

VIL ≤ 0.3V, VIH ≥ 0.8V

× VDD

7

Standby current in non power down

IDD2N

20

mA

CKE, /CS = VIH,

tCK = tCK (min.)

VIL ≤ 0.3V, VIH ≥ 0.8V

× VDD

4

Standby current in non power down

(input signal stable)

IDD2NS

9

mA

CKE = VIH, tCK =

∞,

VIL ≤ 0.3V, VIH ≥ 0.8V

× VDD

8

Active standby current in power down

IDD3P

4

mA

CKE ≤ VIL,

tCK = tCK (min.)

VIL ≤ 0.3V, VIH ≥ 0.8V

× VDD

1, 2, 6

Active standby current in power down

(input signal stable)

IDD3PS

3

mA

CKE ≤ VIL, tCK =

∞

VIL ≤ 0.3V, VIH ≥ 0.8V

× VDD

2, 7

Active standby current in non power down IDD3N

20

mA

CKE, /CS = VIH,

tCK = tCK (min.)

VIL ≤ 0.3V, VIH ≥ 0.8V

× VDD

1, 2, 4

Active standby current in non power down

(input signal stable)

IDD3NS

15

mA

CKE = VIH, tCK =

∞,

VIL ≤ 0.3V, VIH ≥ 0.8V

× VDD

2, 8

Burst operating current

IDD4

70

mA

tCK = tCK (min.),

BL = 4

VIL ≤ 0.3V, VIH ≥ 0.8V

× VDD

1, 2, 5

Refresh current

IDD5

160

mA

tRC = tRC (min.)

VIL ≤ 0.3V, VIH ≥ 0.8V

× VDD

3

Self refresh current

IDD6

3

mA

VIL ≤ 0.3V, VIH ≥ 0.8V

× VDD

Notes: 1. IDD depends on output load condition when the device is selected. IDD (max.) is specified at the output

open condition.

2. One bank operation.

3. Input signals are changed once per one clock.

4. Input signals are changed once per two clocks.

5. Input signals are changed once per four clocks.

6. After power down mode, CLK operating current.

7. After power down mode, no CLK operating current.

8. Input signals are VIH or VIL fixed.

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