EDE5116ABSE datasheet(8/66 Pages) ELPIDA

Part #	EDE5116ABSE

Description	512M bits DDR2 SDRAM

Download	66 Pages

Scroll/Zoom	100%

Manufacturer	ELPIDA [Elpida Memory]

Direct Link	http://www.elpida.com/en

Logo

8 / 66 page

EDE5104ABSE, EDE5108ABSE, EDE5116ABSE

Data Sheet E0323E90 (Ver. 9.0)

8

max.

Parameter

Symbol Grade

× 4

× 8

× 16

Unit Test condition

Auto-refresh current

IDD5

-5C

-4A

250

230

250

230

250

230

mA

tCK = tCK (IDD);

Refresh command at every tRFC (IDD) interval;

CKE is H, /CS is H between valid commands;

Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

Self-refresh current

IDD6

6

mA

Self Refresh Mode;

CK and /CK at 0V;

CKE

≤ 0.2V;

Other control and address bus inputs are FLOATING;

Data bus inputs are FLOATING

Operating current

(Bank interleaving)

IDD7

-5C

-4A

300

280

320

300

500

480

mA

all bank interleaving reads, IOUT = 0mA;

BL = 4, CL = CL(IDD), AL = tRCD (IDD)

−1

× tCK (IDD);

tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD(IDD),

tRCD = 1

× tCK (IDD);

CKE is H, CS is H between valid commands;

Address bus inputs are STABLE during DESELECTs;

Data pattern is same as IDD4W;

Notes: 1. IDD specifications are tested after the device is properly initialized.

2. Input slew rate is specified by AC Input Test Condition.

3. IDD parameters are specified with ODT disabled.

4. Data bus consists of DQ, DM, DQS, /DQS, RDQS, /RDQS, LDQS, /LDQS, UDQS, and /UDQS. IDD

values must be met with all combinations of EMRS bits 10 and 11.

5. Definitions for IDD

L is defined as VIN

≤ VIL (AC) (max.)

H is defined as VIN

≥ VIH (AC) (min.)

STABLE is defined as inputs stable at an H or L level

FLOATING is defined as inputs at VREF = VDDQ/2

SWITCHING is defined as:

inputs changing between H and L every other clock cycle (once per two clocks) for address and control

signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals

not including masks or strobes.

6. Refer to AC Timing for IDD Test Conditions.

AC Timing for IDD Test Conditions

For purposes of IDD testing, the following parameters are to be utilized.

DDR2-533

DDR2-400

Parameter

4-4-4

3-3-3

Unit

CL(IDD)

4

3

tCK

tRCD(IDD)

15

ns

tRC(IDD)

55

ns

tRRD(IDD)-

×4/×8

7.5

ns

tRRD(IDD)-

×16

10

ns

tCK(IDD)

3.75

5

ns

tRAS(min.)(IDD)

40

ns

tRAS(max.)(IDD)

70000

ns

tRP(IDD)

15

ns

tRFC(IDD)

105

ns

Similar Part No. - EDE5116ABSE

Manufacturer	Part #	Datasheet	Description
Elpida Memory	EDE5116AFSE	681Kb / 65P	512M bits DDR2 SDRAM (32M words x 16 bits)
	EDE5116AFSE-4A-E	681Kb / 65P	512M bits DDR2 SDRAM (32M words x 16 bits)
	EDE5116AFSE-5C-E	681Kb / 65P	512M bits DDR2 SDRAM (32M words x 16 bits)
	EDE5116AFSE-6E-E	681Kb / 65P	512M bits DDR2 SDRAM (32M words x 16 bits)
	EDE5116AHBG-4A-E	788Kb / 75P	512M bits DDR2 SDRAM

More results

Similar Description - EDE5116ABSE

Manufacturer	Part #	Datasheet	Description
Elpida Memory	EDE5104AJSE	754Kb / 77P	512M bits DDR2 SDRAM
	EDE5108AHBG	788Kb / 75P	512M bits DDR2 SDRAM
	EDE5104AGSE	592Kb / 74P	512M bits DDR2 SDRAM
	EDE5108AJBG	620Kb / 77P	512M bits DDR2 SDRAM
	EDE5108AESK	680Kb / 65P	512M bits DDR2 SDRAM
	EDE5104AHSE	562Kb / 69P	512M bits DDR2 SDRAM
	EDE5108AHSE	880Kb / 81P	512M bits DDR2 SDRAM
	EDE5104AJBG	814Kb / 77P	512M bits DDR2 SDRAM
	EDE5132BABG	756Kb / 74P	512M bits DDR2 SDRAM
	EDE5132AABG	735Kb / 74P	512M bits DDR2 SDRAM

More results

EDE5116ABSE Datasheet(PDF) 8 Page - Elpida Memory

EDE5116ABSE Datasheet(HTML) 8 Page - Elpida Memory

Similar Part No. - EDE5116ABSE

Similar Description - EDE5116ABSE

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

Datasheet Download

Link URL