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EDD5116AFTA-7B-E Datasheet(PDF) 9 Page - Elpida Memory |
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EDD5116AFTA-7B-E Datasheet(HTML) 9 Page - Elpida Memory |
9 / 49 page EDD5108AFTA, EDD5116AFTA Data Sheet E0699E20 (Ver. 2.0) 9 Timing Parameter Measured in Clock Cycle Number of clock cycle tCK 6ns 7.5ns Parameter Symbol min. max. min. max. Unit Write to pre-charge command delay (same bank) tWPD 4 + BL/2 — 3 + BL/2 — tCK Read to pre-charge command delay (same bank) tRPD BL/2 — BL/2 — tCK Write to read command delay (to input all data) tWRD 2 + BL/2 — 2 + BL/2 — tCK Burst stop command to write command delay (CL = 2) tBSTW — — 2 — tCK (CL = 2.5) tBSTW 3 — 3 — tCK Burst stop command to DQ High-Z (CL = 2) tBSTZ — — 2 2 tCK (CL = 2.5) tBSTZ 2.5 2.5 2.5 2.5 tCK Read command to write command delay (to output all data) (CL = 2) tRWD — — 2 + BL/2 — tCK (CL = 2.5) tRWD 3 + BL/2 — 3 + BL/2 — tCK Pre-charge command to High-Z (CL = 2) tHZP — — 2 2 tCK (CL = 2.5) tHZP 2.5 2.5 2.5 2.5 tCK Write command to data in latency tWCD 1 1 1 1 tCK Write recovery time tWR 3 — 2 — tCK DM to data in latency tDMD 0 0 0 0 tCK Mode register set command cycle time tMRD 2 — 2 — tCK Self refresh exit to non-read command tSNR 12 — 10 — tCK Self refresh exit to read command tSRD 200 — 200 — tCK Power down entry tPDEN 1 1 1 1 tCK Power down exit to command input tPDEX 1 — 1 — tCK |
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