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EBE51ED8AGFA-5C-E Datasheet(PDF) 8 Page - Elpida Memory |
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EBE51ED8AGFA-5C-E Datasheet(HTML) 8 Page - Elpida Memory |
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8 / 23 page  EBE51ED8AGFA Data Sheet E0783E20 (Ver. 2.0) 8 Block Diagram RS1 DQS8 RS1 /DQS8 RS1 DM3 DQS3 RS1 DM0 BA0 to BA1: SDRAMs (D0 to D8) A0 to A13: SDRAMs (D0 to D8) BA0 to BA1 /RAS: SDRAMs (D0 to D8) CKE0 CKE: SDRAMs (D0 to D8) ODT0 ODT:SDRAMs (D0 to D8) VDDSPD SPD VREF SDRAMs (D0 to D8) VDD SDRAMs (D0 to D8) VSS SDRAMs (D0 to D8) Serial PD SDA A0 A1 A2 WP SCL SA0 SA1 SA2 SDA SCL Notes : 1. DQ wiring maybe changed within a byte. 2. DQ, DQS, /DQS, ODT, DM, CKE, /CS relationships must be meintained as shown. 3. Refer to the appropriate clock wiring topology under the DIMM wiring details section of this document. /DQS0 DQ0 to DQ7 8 D1 /RAS /CAS /WE A0 to A13 /CAS: SDRAMs (D0 to D8) /WE: SDRAMs (D0 to D8) /CS0 D5 D4 /CS DQS DM DQ0 to DQ7 RS1 RS1 RS1 RS1 DM4 /DQS4 DQS0 RS1 RS1 DQS4 RS1 RS1 DQ8 to DQ15 8 RS1 DQ32 to DQ39 8 RS1 DQ40 to DQ47 8 RS1 DQ16 to DQ23 8 D3 D6 D7 RS1 DQ24 to DQ31 8 RS1 DM5 DQS5 RS1 /DQS5 RS1 RS1 DM6 DQS6 RS1 RS1 DM7 DQS7 RS1 /DQS3 RS1 /DQS7 RS1 DM1 DQS1 RS1 /DQS1 RS1 RS1 DM2 DQS2 RS1 RS1 /DQS6 RS1 /DQS2 RS1 RS2 RS2 RS2 RS2 RS2 DQ48 to DQ55 8 RS1 DQ56 to DQ63 8 RS1 D2 * D0 to D7 : 512M bits DDR2 SDRAM U0 : 2k bits EEPROM Rs1 : 22 Ω Rs2 : 10 Ω /CS DQS DM /CS DQS /DQS /DQS /DQS /DQS /DQS /DQS /DQS DM /CS DQS DM DQ0 to DQ7 /CS DQS DM DQ0 to DQ7 /CS DQS DM DQ0 to DQ7 /CS DQS DM DQ0 to DQ7 DQ0 to DQ7 DQ0 to DQ7 D0 /CS DQS DM DQ0 to DQ7 /DQS U0 D8 DQ0 to DQ7 /DQS /CS DQS DM8 CB0 to CB7 8 RS1 RS1 DM |
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