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M5M54R04AJ-12 Datasheet(PDF) 2 Page - Mitsubishi Electric Semiconductor |
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M5M54R04AJ-12 Datasheet(HTML) 2 Page - Mitsubishi Electric Semiconductor |
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2 / 6 page  M5M54R04AJ-10,-12,-15 MITSUBISHI ELECTRIC MITSUBISHI LSIs 4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM VI(S)=VIL other inpus=VIH or VIL Output-open(duty 100%) VI= 0 ~ Vcc - 2.0 ~ VCC Operating temperature V cc VI VO Pd Topr Tstg V V V mW - 2.0 ~ 4.6 1000 0 ~ 70 - 65 ~ 150 Ta=25°C 2 Icc S W OE H Mode Non selection Stand by ABSOLUTE MAXIMUM RATINGS Parameter Supply voltage Input voltage Output voltage Power dissipation Storage temperature(bias) Symbol Unit Conditions With respect to GND Ratings DQ High-impedance * Pulse width ≤3ns, In case of DC: - 0.5V The operation mode of the M5M54R04AJ is determined by a combination of the device control inputs S, W and OE. Each mode is summarized in the function table. A write cycle is executed whenever the low level W overlaps with the low level S. The address must be set-up before the write cycle and must be stable during the entire cycle. The data is latched into a cell on the trailing edge of W or S, whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. The output enable input OE directly controls the output stage. Setting the OE at a high level, the output stage is in a high impedance state, and the data bus contention problem in the write cycle is eliminated. A read cycle is excuted by setting W at a high level and OE at a low level while S are in an active state (S=L). When setting S at high level, the chip is in a non- selectable mode in which both reading and writing are disable. In this mode, the output stage is in a high- impedance state, allowing OR-tie with other chips and memory expansion by S. Signal-S controls the power-down feature. When S goes high, power dissapation is reduced extremely. The access time from S is equivalent to the address access time. FUNCTION - 2.0 ~ VCC+0.5 X X DC ELECTRICAL CHARACTERISTICS (Ta=0 ~ 70°C, Vcc=3.3V ,unless otherwise noted) VIH VIL VOH V V V Vcc+0.3 0.8 2.0 2.4 VOL 0.4 IOH= - 4mA Symbol Parameter Max Typ Limits Min Condition Unit High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage VI(S)=VIH VI/O= 0 ~ Vcc I I I CC1 I CC2 I CC3 mA mA 190 I OZ 2 2 uA uA VI(S)=Vcc ≥0.2V other inputs VI ≤0.2V or VI ≥Vcc - 0.2V AC DC 10 Input current Active supply current (TTL level) Stand by current (TTL level) Output current in off-state Stand by current IOL = 8mA VI(S)=VIH Tstg(bias) Storage temperature - 10 ~ 85 FUNCTION TABLE 90 180 160 10ns cycle V L Write Active Din L X L Read Active Dout H L L Active High-impedance H H 12ns cycle 15ns cycle mA 90 AC DC 40 70 60 10ns cycle 12ns cycle 15ns cycle +10% - 5% * * * °C °C °C Note 1: Direction for current flowing into an IC is positive (no mark). |
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Similar Description - M5M54R04AJ-12 |
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