Quick-Start Guide

This section describes how to configure a MAX6966 or

MAX6967 on power-up.

Software engineers can use this section as a plain-text

guide to the device’s initialization routine. Hardware

engineers can use this section to get a quick overview

of the device’s capabilities and feature tradeoffs:

1) Before power-up, all 10 I/O ports P0 to P9 are high

impedance. They may be connected to inputs up to

+7V or loads connected to independent rails up to

+7V. The SPI bus inputs (SCLK, CS, DIN) are not

overvoltage protected, and must not be driven from

a voltage higher than V+.

2) After power-up, all 10 I/O ports P0 to P9 remain

high impedance. They may be connected to inputs

up to +7V or loads connected to V+ or independent

rails up to +7V. The ports are not configured as logic

inputs even though the ports are high impedance.

The device is in shutdown mode, and draws mini-

mum supply current regardless of I/O ports connec-

tions.

3) Decide whether the DOUT/OSC pin will be used

as SPI data output or PWM clock input, and

choose the MAX6966 or MAX6967 accordingly. If

any ports are used as logic input, or if the applica-

tion needs read-after-write validation, then

DOUT/OSC needs to be configured as DOUT. Note

that both the MAX6966 and MAX6967 can configure

DOUT/OSC as either DOUT output or OSC clock

input; the only difference is the power-up default.

4) Allocate port functionality for the 10 I/O ports. All

ports have the same features, so allocate ports for

either software convenience or board-routing rea-

sons. Any port can be constant-current LED drivers

(static or PWM), an open-drain logic output, or a

logic input. If fewer than 10 ports are used as con-

stant-current drivers, see the Applications

Information section for details on how to optimize the

PWM phasing to minimize load supply-current mod-

ulation.

5) Decide how to implement LED intensity control.

The MAX6966/MAX6967 provide:

• Individual 8-bit PWM control per constant-current

output

• Individual 1-bit analog control (half/full) per

constant-current output

• Global 3-bit analog control, which applies to all

constant-current outputs

10-Port Constant-Current LED Drivers and I/O

Expanders with PWM Intensity Control

6

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Pin Description

PIN

QSOP

TQFN

NAME

FUNCTION

1

15

SCLK

Serial-Clock Input. On SCLK’s rising edge, data shifts into the internal shift register. On SCLK’s

falling edge, data is clocked out of DOUT. SCLK is active only while CS is low.

216

CS

Chip-Select Input. Serial data is loaded into the shift register while CS is low. The most recent 16

bits of data latch on CS’s rising edge.

3–7,

9-13

1–5,

7-11

P0-P9

I/O Ports. P0 to P9 can be configured as open-drain current-sink outputs rated at 20mA

maximum, or as CMOS-logic inputs, or as open-drain logic outputs. Loads should be connected

to a supply voltage no higher than 7V.

8

6

GND

Ground

14

12

DOUT/OSC

Serial-Data Output. The data into DIN is valid at DOUT 15.5 clock cycles later. Use this pin to

daisy-chain several devices or allow data readback. Output is push-pull.

OSC Input. Apply a square-wave CMOS clock up to 100kHz as alternate PWM clock source.

The MAX6966 powers up with DOUT/OSC defaulting as DOUT output.

The MAX6967 powers up with DOUT/OSC defaulting as OSC input.

15

13

DIN

Serial-Data Input. Data from DIN loads into the internal 16-bit shift register on SCLK’s rising

edge.

16

14

V+

Positive Supply Voltage. Bypass V+ to GND with a 0.1µF ceramic capacitor.

—

PAD

Exposed

pad

Exposed Pad on Package Underside. Connect to GND.