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LPC47M112 Datasheet(PDF) 75 Page - SMSC Corporation |
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LPC47M112 Datasheet(HTML) 75 Page - SMSC Corporation |
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75 / 208 page  Enhanced Super I/O Controller with LPC Interface Datasheet SMSC DS – LPC47M112 Page 75 Rev. 02/02/2005 REGISTER ADDRESS* REGISTER NAME REGISTER SYMBOL BIT 0 BIT 1 ADDR = 7 Scratch Register (Note 4) SCR Bit 0 Bit 1 ADDR = 0 DLAB = 1 Divisor Latch (LS) DDL Bit 0 Bit 1 ADDR = 1 DLAB = 1 Divisor Latch (MS) DLM Bit 8 Bit 9 *DLAB is Bit 7 of the Line Control Register (ADDR = 3). Note 1: Bit 0 is the least significant bit. It is the first bit serially transmitted or received. Note 2: When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty. Table 32 - Register Summary for an Individual UART Channel (continued) BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7 Enable Receiver Line Status Interrupt (ELSI) Enable MODEM Status Interrupt (EMSI) 0 0 0 0 Interrupt ID Bit Interrupt ID Bit (Note 5) 0 0 FIFOs Enabled (Note 5) FIFOs Enabled (Note 5) XMIT FIFO Reset DMA Mode Select (Note 6) Reserved Reserved RCVR Trigger LSB RCVR Trigger MSB Number of Stop Bits (STB) Parity Enable (PEN) Even Parity Select (EPS) Stick Parity Set Break Divisor Latch Access Bit (DLAB) OUT1 (Note 3) OUT2 (Note 3) Loop 0 0 0 Parity Error (PE) Framing Error (FE) Break Interrupt (BI) Transmitter Holding Register (THRE) Transmitter Empty (TEMT) (Note 2) Error in RCVR FIFO (Note 5) Trailing Edge Ring Indicator (TERI) Delta Data Carrier Detect (DDCD) Clear to Send (CTS) Data Set Ready (DSR) Ring Indicator (RI) Data Carrier Detect (DCD) Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15 Note 3: This bit no longer has a pin associated with it. Note 4: When operating in the XT mode, this register is not available. Note 5: These bits are always zero in the non-FIFO mode. Note 6: Writing a one to this bit has no effect. DMA modes are not supported in this chip. Note 7: The UART1 and UART2 FCR’s are shadowed in the UART1 FIFO Control Shadow Register (runtime register at offset 0x20) and UART2 FIFO Control Shadow Register (runtime register at offset 0x21). |
Similar Part No. - LPC47M112 |
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Similar Description - LPC47M112 |
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