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IDT72V2111 Datasheet(PDF) 9 Page - Integrated Device Technology |
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IDT72V2111 Datasheet(HTML) 9 Page - Integrated Device Technology |
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9 / 27 page  9 COMMERCIAL AND INDUSTRIAL TEMPERATURERANGES IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS SUPERSYNC FIFOTM 262,144 x 9, 524,288 x 9 Figure 3. Offset Register Location and Default Values EMPTY OFFSET (LSB) REGISTER 87 0 IDT72V2101 (262,144 x 9 BIT) FULL OFFSET (LSB) REGISTER 8 7 0 FULL OFFSET (MID-BYTE) REGISTER 87 0 DEFAULT VALUE 7FH if LD is LOW at Master Reset FFH if LD is HIGH at Master Reset DEFAULT VALUE 7FH if LD is LOW at Master Reset FFH if LD is HIGH at Master Reset DEFAULT VALUE 00H if LD is LOW at Master Reset 03H if LD is HIGH at Master Reset EMPTY OFFSET (MID-BYTE) REGISTER 87 0 DEFAULT VALUE 00H if LD is LOW at Master Reset 03H if LD is HIGH at Master Reset EMPTY OFFSET (LSB) REGISTER 87 0 4669 drw 06 IDT72V2111 (524,288 x 9 BIT) FULL OFFSET (LSB) REGISTER 87 0 FULL OFFSET (MID-BYTE) REGISTER 8 7 0 DEFAULT VALUE 7FH if LD is LOW at Master Reset FFH if LD is HIGH at Master Reset DEFAULT VALUE 7FH if LD is LOW at Master Reset FFH if LD is HIGH at Master Reset DEFAULT VALUE 00H if LD is LOW at Master Reset 03H if LD is HIGH at Master Reset EMPTY OFFSET (MID-BYTE) REGISTER 87 0 DEFAULT VALUE 00H if LD is LOW at Master Reset 03H if LD is HIGH at Master Reset 83 0 82 1 0 8 2 3 0 2 82 1 0 DEFAULT 0H EMPTY OFFSET (MSB) REGISTER DEFAULT 0H FULL OFFSET (MSB) REGISTER DEFAULT 0H EMPTY OFFSET (MSB) REGISTER DEFAULT 0H FULL OFFSET (MSB) REGISTER |
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