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TPS23750 Datasheet(PDF) 9 Page - Texas Instruments

Part No. TPS23750
Description  INTEGRATED 100-V IEEE 802.3af PD AND DC/DC CONTROLLER
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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DETAILED DESCRIPTION
TPS23750
TPS23770
SLVS590A – JULY 2005 – REVISED AUGUST 2005
AUX – This pin is the junction between the internal 10 V converter-bias regulator, the gate driver supply, and the
5-V regulator that powers the rest of the converter control circuit. Voltage may be applied to this pin during
normal converter operation to improve efficiency and reduce the TPS23750 temperature rise. A UVLO of about
8 V monitors VAUX-COM to prevent operation with inadequate or weak bias. A converter overvoltage lockout
protects the IC when a bias winding is used and VAUX rises above 17.5 V.
A low ESR bypass capacitor of at least 0.8
µF must be connected from AUX to COM.
BL – This pin selects the desired blanking operation. The blanking function prevents the sensed MOSFET
current from tripping the PWM and current limit comparators for a predetermined period after the GATE switches
high. This prevents the comparators from being falsely triggered by the gate drive current and recovery currents
in the external power rectifiers. The recovery currents are strongly influenced by the topology, device selection,
and device parasitics. The current limit comparator, logic, and gate driver account for the minimum delay which is
obtained with the BL pin open. There are two preset delay choices, as shown below. Shorter periods may be
obtained by leaving BL open and using an RC filter.
Table 1. BL Connections
BL CONNECTION
BLANKING OPERATION
Open
None (Minimum current-sense loop delay)
RSN
Minimum plus 70 ns
VBIAS
Minimum plus 105 ns
CLASS – Classification is a PoE function implemented by means of an external resistor, RCLASS, connected
between CLASS and VSS. Current is drawn from VDD through RCLASS for input voltages between 13 V and 21 V.
Classification allows the PD to indicate the required average power requirements to the PSE as shown in
Table 2. Classification
802.3af CLASS
PD POWER
RCLASS
CURRENT
CLASS
NOTE
(W)
(
Ω)
LIMITS
(mA)
0
0.44 – 12.95
4420
±1%
0 – 4
Default class
1
0.44 – 3.84
953
±1%
9 – 12
2
3.84 – 6.49
549
±1%
17 – 20
3
6.49 – 12.95
357
±1%
26 – 30
4
Reserved
255
±1%
36 – 44
Treated like class 0
Approximately 10 V is applied to the CLASS resistor for up to 75 ms. The resistor’s wattage rating need only be
based on this transient condition.
The CLASS pin must not be shorted to ground. The recommended CLASS 0 resistor serves as a bleeder for
capacitance connected around the TPS23750 after power is removed.
COM – Switching regulator gate driver return. This signal is internally separated from RTN and RSN to minimize
noise coupling, but it should always be connected to RSN and RTN on the circuit board.
COMP – The TPS23750 is a traditional current-mode controller. The COMP pin represents the junction between
the voltage control loop’s error amplifier output and the current control loop’s reference input. The name refers to
the traditional connection of loop compensation components, which are connected between COMP and FB.
MODE alters the function of COMP. If MODE is tied to RTN, the internal error amplifier is enabled. If MODE is
tied to VBIAS, the internal amplifier disconnects from COMP, allowing an optocoupler to be fed directly into the
PWM comparator circuit. The COMP pin should only be driven between RTN and VBIAS when in this mode. Tie
FB to RTN when the amplifier is disabled.
The current-mode control range includes COMP voltages between 1.35 V and just under 4 V. Converter
switching is inhibited for COMP voltages below 1.35 V. COMP voltages higher than of 4.1 V cause the TMR
circuit to begin hiccup operation. COMP is forced low during a hiccup-cycle off period when the internal error
amplifier is used.
9



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