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MC74 Datasheet(PDF) 4 Page - ON Semiconductor |
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MC74 Datasheet(HTML) 4 Page - ON Semiconductor |
4 / 12 page MC74 http://onsemi.com 4 DETAILED OPERATING DESCRIPTION The MC74 acquires and converts temperature information from its integrated solid state sensor with a basic accuracy of ±1°C . It stores the data in an internal register which is read through the serial port. The system interface is a slave SMBus. The temperature data can be read at any time through the SMBus port. Eight SMBus addresses are programmable for the MC74, which allows for a multi–sensor configuration. Also, there is low–power Standby mode where temperature acquisition is suspended. Standby Mode The MC74 allows the host to put it into a low power (IDD = 5 µA, typical) Standby mode. In this mode, the A/D converter is halted and the temperature data registers are frozen. The SMBus port operates normally. Standby mode is enabled by setting the SHDN bit in the CONFIG register. The table below summarizes this operation. Standby Mode Operation SHDN Bit Operating Mode 0 Normal 1 Standby SMBus Slave Address The MC74 is internally programmed to have a default SMBus address value of 1001 101b. Seven other addresses are available by custom order (contact factory). SERIAL PORT OPERATION The Serial Clock input (SCL) and bi–directional data port (SDA) form a 2–wire bi–directional serial port for programming and interrogating the MC74. The following conventions are used in this bus architecture: MC74 Serial Bus Conventions Term Explanation Transmitter The device sending data to the bus. Receiver The device receiving data from the bus. Master The device which controls the bus: initiating transfers (START), generating the clock, and terminating transfers (STOP). Slave The device addressed by the master. Start A unique condition signaling the beginning of a transfer indicated by SDA falling (High — Low) while SCL is high. Stop A unique condition signaling the end of a transfer indicated by SDA rising (Low — High) while SCL is high. ACK A receiver acknowledges the receipt of each byte with this unique condition. The receiver drives SDA low during SCL high of the ACK clock–pulse. The Master pro- vides the clock pulse for the ACK cycle. Busy Communication is not possible because the bus is in use. NOT Busy When the bus is idle, both SDA and SCL will remain high. Data Valid The state of SDA must remain stable dur- ing the High period of SCL in order for a data bit to be considered valid. SDA only changes state while SCL is low during nor- mal data transfers (see Start and Stop conditions). All transfers take place under control of a host, usually a CPU or microcontroller, acting as the Master which provides the clock signal for all transfers. The MC74 always operates as a Slave. The serial protocol is illustrated in Figure 1. All data transfers have two phases; all bytes are transferred MSB first. Accesses are initiated by a start condition (START), followed by a device address byte and one or more data bytes. The device address byte includes a Read/Write selection bit. Each access must be terminated by a Stop Condition (STOP). A convention called Acknowledge (ACK) confirms receipt of each byte. Note that SDA can change only during periods when SCL is LOW (SDA changes while SCL is HIGH are reserved for Start and Stop Conditions). |
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