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M.tec
TTS3816B4E
Revision_1.1
1
TwinMOS Technologies Inc.
Sep. 2000
2M x 16Bit x 4 Banks synchronous DRAM
GENERAL DESCRIPTION
The TTS3816B4E is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 8 x 1,048,576 words by 16 bits,
fabricated with M’tec high performance CMOS technology. Synchronous design allows precise cycle control with the use of
system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and
programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system
applications.
FEATURES
•
JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four-banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
•
All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (4K cycle)
ORDERING INFORMATION
Part No.
Max Freq.
Interface
Package
TTS3816B4E-7
100MHz 2-2-2
TTS3816B4E-6
133MHz 3-3-3
TTS3816B4E-6A
100MHz 2-3-3
TTS3816B4E-6B
133MHz 2-3-2
TTS3816B4E-6C
133MHz 2-2-2
TTS3816B4E-6D
150MHz 3-3-3
TTS3816B4E-6E
166MHz 3-3-3
LVTTL
54
TSOP(II)
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