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Pin Number
PLCC
DIP
QFP
Mnemonic
Type
Description
43
39
4
TR
O
†
Trigger asserts when one of the trigger conditions is satisfied.
33
30
38
CONT*
O
†
Controller asserts when the NAT9914 is Controller-In-Charge.
44
40
5
VDD
–
Power pin – +5 V (±5%)
22
20
27
VSS
–
Ground pin – 0 V
1, 18,
–
1, 6,
NC
–
No connect
28,40
23, 33
OC= Open collector.
† The pin contains an internal pull-up resistor of 25 k
Ω to 100 kΩ.
* Active low.
†† In controller applications where the CLK signal frequency is > 8 MHz, IFC* should be pulled up with a 4.7 k
Ω resistor.
††† RS0 and RS1 contain an internal pull-up resistor of 25 k
Ω to 100 kΩ. RS2 does not contain an internal pull-up or pull-down resistor.
IEEE 488.2 Controller Chip
National Instruments
Tel: (512) 794-0100 • Fax: (512) 683-9300 • info@ni.com • ni.com/gpib
3
Interface
Functions
SH1
AH1
T5/TE5
L3/LE3
SR1
RL1
PP1/PP2
DC1
DT1
C1-C5
RSV Gen
EOI Gen
STB Out
SYNC
D(7-0)
CE*
RS(2-0)
DBIN
WE*
ACCRQ*
ACCGR*
INT*
CLK
Data-In
Command Pass Through
Command/Data Out
Address Status
Address Mode
Address
End-of-String
Interrupt Mask 0, 1, 2
Interrupt Status 0, 1, 2
Serial Poll
Parallel Poll
Aux A, B, E, F, G, I
SASR
Version
Auxiliary
Command Decoder
RESET*
Bus Status
and Control
DIO(8-1)*
GPIB
Control
CONT*
TE
TR
Internal Count
Internal Count 2
Message
Decoder
Read/
Write
Control
Figure 4. NAT9914 Block Diagram