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IDT74ALVCH162721PA Datasheet(PDF) 2 Page - Integrated Device Technology |
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IDT74ALVCH162721PA Datasheet(HTML) 2 Page - Integrated Device Technology |
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2 / 6 page  2 EXTENDED COMMERCIAL TEMPERATURE RANGE IDT74ALVCH162721 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS GND GND GND SO56-1 SO56-2 SO56-3 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 48 49 50 51 52 53 54 55 56 1 GND GND GND 25 26 27 28 32 31 30 29 CLK D1 D2 OE Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 Q18 Q19 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 VCC D17 D18 D19 GND VCC D20 CLKEN VCC VCC GND Q20 NC ABSOLUTE MAXIMUM RATING (1) Symbol Description Max. Unit VTERM(2) Terminal Voltage with Respect to GND – 0.5 to + 4.6 V VTERM(3) Terminal Voltage with Respect to GND – 0.5 to VCC + 0.5 V TSTG Storage Temperature – 65 to + 150 °C IOUT DC Output Current – 50 to + 50 mA IIK Continuous Clamp Current, VI < 0 or VI > VCC ± 50 mA IOK Continuous Clamp Current, VO < 0 – 50 mA ICC ISS Continuous Current through each VCC or GND ±100 mA NEW16link NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC. CAPACITANCE (TA = +25oC, f = 1.0MHz) Symbol Parameter(1) Conditions Typ. Max. Unit CIN Input Capacitance VIN = 0V 5 7 pF COUT Output Capacitance VOUT = 0V 7 9 pF CI/O I/O Port Capacitance VIN = 0V 7 9 pF NEW16link NOTE: 1. As applicable to the device type. PIN CONFIGURATION SSOP/ TSSOP/TVSOP TOP VIEW FUNCTION TABLE (each flip-flop)(1) NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High-Impedance ↑ = LOW-to-HIGH Transition Q0 = Output level before the indicated steady-state input conditions were established. PIN DESCRIPTION NOTE: 1. These pins have “Bus-Hold.” All other pins are standard inputs, outputs, or I/Os. Pin Names Description OE 3–State Output Enable Input (Active LOW) Dx Data Inputs (1) Qx 3-State Outputs CLK Clock Input CLKEN Clock Enable Input (Active LOW) NC No Internal Connection Inputs Output OE CLKEN CLK Dx Qx L H XXQ0 LL ↑ HH LL ↑ LL L L L or H X Q0 HX X X Z |
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