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IDT74ALVCH162721 Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT74ALVCH162721 Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 6 page 1 EXTENDED COMMERCIAL TEMPERATURE RANGE IDT74ALVCH162721 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS MARCH 1999 1999 Integrated Device Technology, Inc. DSC-4566/- c IDT74ALVCH162721 EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS AND BUS-HOLD FEATURES: – 0.5 MICRON CMOS Technology –Typical tSK(0) (Output Skew) < 250ps – ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) – 0.635mm pitch SSOP, 0.50mm pitch TSSOP, and 0.40mm pitch TVSOP packages – Extended commercial range of – 40°C to + 85°C –VCC = 3.3V ± 0.3V, Normal Range –VCC = 2.7V to 3.6V, Extended Range –VCC = 2.5V ± 0.2V – CMOS power levels (0.4µ W typ. static) – Rail-to-Rail output swing for increased noise margin APPLICATIONS: • 3.3V High Speed Systems • 3.3V and lower voltage computing systems Functional Block Diagram DESCRIPTION: This 20-bit flip-flop is built using advanced dual metal CMOS technol- ogy. The 20 flip-flops of the ALVCH162721 are edge-triggered D-type flip-flops with qualified clock storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs if the clock-enable (CLKEN) input is low. If CLKEN is high, no data is stored. A buffered output-enable (OE) input places the 20 outputs in either a normal logic state (high or low) or a high-impedance state. In the high- impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup compo- nents. OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The ALVCH162721 has series resistors in the device output structure which will significantly reduce line noise when used with light loads. This driver has been designed to drive ±12mA at the designated threshold levels. The ALVCH162721 has “bus-hold” which retains the inputs’ last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistor. Drive Features for ALVCH162721: – Balanced Output Drivers: ±12mA – Low switching noise CLK OE CLKEN D1 1 56 29 55 CE C1 1D 2 Q1 To 19 Other Channels |
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