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IDT74ALVC1G00 Datasheet(PDF) 5 Page - Integrated Device Technology |
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IDT74ALVC1G00 Datasheet(HTML) 5 Page - Integrated Device Technology |
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5 / 6 page  5 EXTENDED COMMERCIAL TEMPERATURE RANGE IDT74ALVC1G00 3.3V CMOS SINGLE 2-INPUT POSITIVE-NAND GATE O pen V LOAD GN D V CC Pulse G enerato r D.U.T. 1000 Ω 10 00 Ω C L RT V IN V OUT (1) ALVC 1G Link DATA IN PU T 0V 0V 0V 0V tREM TIM IN G IN PU T AS YNCHRO N OU S CO NTRO L SY NCHRO N OU S CO NTRO L tSU tH tSU tH VIH VT VIH VT VIH VT VIH VT LO W -H IGH -LOW PU LSE H IGH -LOW -H IGH PU LSE VT tW VT ALVC 1G Link SA M E PH A SE IN PU T TR A N SIT IO N O PPO SITE PH A SE IN PU T TR A N SIT IO N 0V 0V VOH VOL tPLH tPHL tPHL tPLH OU TPU T VIH V T VT VIH VT CO NTRO L IN PU T tPLZ 0V OU TPU T NO RMA LLY LO W tPZH 0V SW ITCH CLO SE D OU TPU T NO RMA LLY HIG H EN A BLE D ISA BLE SW ITCH OPEN tPHZ 0V VLZ V OH VT VT tPZL VLOAD/2 VLOAD/2 VIH VT VOL VHZ ALVC 1G Link ALVC 1G Link ALVC 1G Link TEST CONDITIONS PROPAGATION DELAY TEST CIRCUITS FOR ALL OUTPUTS ENABLE AND DISABLE TIMES SET-UP, HOLD, AND RELEASE TIMES SWITCH POSITION PULSE WIDTH 1.8V ±±±±± 0.15V TEST CIRCUITS AND WAVEFORMS: Symbol VCC(1)= 1.8V ± 0.15V Unit VLOAD 2 x VCC V VIH VCC V VT VCC / 2 V VLZ 150 mV VHZ 150 mV CL 30 pF ALVC 1G Link DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. Test Switch Open Drain Disable Low Enable Low VLOAD Disable High Enable High GND All Other tests Open ALVC 1G Link NOTE: 1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns. |
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