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A63L0636E-3.8F Datasheet(PDF) 2 Page - AMIC Technology |
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A63L0636E-3.8F Datasheet(HTML) 2 Page - AMIC Technology |
2 / 17 page A63L0636 1M X 36 Bit Synchronous High Speed SRAM with Preliminary Burst Counter and Pipelined Data Output PRELIMINARY (July, 2005, Version 0.0) 1 AMIC Technology, Corp. Features Fast access times: 2.6/2.8/3.2/3.5/3.8/4.2 ns (250/227/200/166/150/133 MHZ) Single +3.3V+10% or +3.3V-5% power supply Synchronous burst function Individual Byte Write control and Global Write Registered output for pipelined applications Three separate chip enables allow wide range of options for CE control, address pipelining Selectable BURST mode SLEEP mode (ZZ pin) provided Available in 100-pin LQFP package General Description The A63L0636E is a high-speed SRAM containing 36M bits of bit synchronous memory, organized as 1024K words by 36 bits. The A63L0636E combines advanced synchronous peripheral circuitry, 2-bit burst control, input registers, output registers and a 1MX36 SRAM core to provide a wide range of data RAM applications. The positive edge triggered single clock input (CLK) controls all synchronous inputs passing through the registers. Synchronous inputs include all addresses (A0 - A19), all data inputs (I/O1 - I/O36), active LOW chip enable ( CE ), two additional chip enables (CE2, CE2 ), burst control inputs ( ADSC , ADSP , ADV ), byte write enables ( BWE , BW1 , BW2 , BW3 , BW4 ) and Global Write ( GW ). Asynchronous inputs include output enable ( OE ), clock (CLK), BURST mode (MODE) and SLEEP mode (ZZ). Burst operations can be initiated with either the address status processor ( ADSP ) or address status controller ( ADSC ) input pin. Subsequent burst sequence burst addresses can be internally generated by the A63L0636E and controlled by the burst advance ( ADV ) pin. Write cycles are internally self-timed and synchronous with the rising edge of the clock (CLK). This feature simplifies the write interface. Individual Byte enables allow individual bytes to be written. BW1 controls I/O1 - I/O9, BW2 controls I/O10 - I/O18, BW3 controls I/O19 - I/O27, and BW4 controls I/O28 - I/O36, all on the condition that BWE is LOW. GW LOW causes all bytes to be written. |
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