A43P26161

PRELIMINARY

(July, 2005, Version 1.1)

10

AMIC Technology, Corp.

Power Up Sequence

1. Apply power and start clock, Attempt to maintain CKE = “H”, DQM = “H” and the other pins are NOP condition at inputs.

2. Maintain stable power, stable clock and NOP input condition for a minimum of 200

µs.

3. Issue precharge commands for all banks of the devices.

4. Issue 2 or more auto-refresh commands.

5. Issue a mode register set command to initialize the mode register. The device is now ready for normal operation.

6. Issue a extended mode register set command to define DS or PASR operating type of the device after normal MRS.

cf.) Sequence of 4 & 5 may be changed.

EMRS cycle is not mandatory and the EMRS command needs to be issued only when DS or PASR is used.

The default state without EMRS command issued is the half driver strength and full array refreshed.

The device is now ready for the operation selected by EMRS.

For operating with DS or PASR, set DS or PASR mode in EMRS setting stage.

In order to adjust another mode in the state of DS or PASR mode, additional EMRS set is required but power up sequence is not

needed again at this time. In that case, all banks have to be in idle state prior to adjusting EMRS set.

Burst Sequence (Burst Length = 4)

Initial address

A1

A0

Sequential

Interleave

0

0

0

1

2

3

0

1

2

3

0

1

1

2

3

0

1

0

3

2

1

0

2

3

0

1

2

3

0

1

1

1

3

0

1

2

3

2

1

0

Burst Sequence (Burst Length = 8)

Initial address

A2

A1

A0

Sequential

Interleave

0

0

0

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

0

1

1

2

3

4

5

6

7

0

1

0

3

2

5

4

7

6

0

1

0

2

3

4

5

6

7

0

1

2

3

0

1

6

7

4

5

0

1

1

3

4

5

6

7

0

1

2

3

2

1

0

7

6

5

4

1

0

0

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

1

0

1

5

6

7

0

1

2

3

4

5

4

7

6

1

0

3

2

1

1

0

6

7

0

1

2

3

4

5

6

7

4

5

2

3

0

1

1

1

1

7

0

1

2

3

4

5

6

7

6

5

4

3

2

1

0