A43E06321G-95UF datasheet(9/46 Pages) AMICC

Part #	A43E06321G-95UF

Description	512K X 32 Bit X 2 Banks Low Power Synchronous DRAM

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Manufacturer	AMICC [AMIC Technology]

Direct Link	http://www.amictechnology.com

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A43E06321

PRELIMINARY

(July, 2005, Version 0.0)

8

AMIC Technology, Corp.

Simplified Truth Table

Command

CKEn-1 CKEn

CS RAS CAS WE DQM BA A10

/AP

A9~A0

Notes

Register

Mode Register Set

H

X

L

X

OP CODE

1,2

Extended Mode Register Set

H

X

L

OP CODE

1,2

Auto Refresh

H

3

Entry

H

L

H

X

3

L

H

3

Refresh

Self

Refresh

Exit

L

H

X

3

Bank Active & Row Addr.

H

X

L

H

X

V

Row Addr.

4

Auto Precharge Disable

L

4

Read &

Column Addr. Auto Precharge Enable

H

X

L

H

L

H

X

V

H

Column

Addr.

4,5

Auto Precharge Disable

L

4

Write &

Column Addr. Auto Precharge Enable

H

X

L

H

L

X

V

H

Column

Addr.

4,5

Burst Stop

H

X

L

H

L

X

6

Bank Selection

V

L

Precharge

Both Banks

H

X

L

H

L

X

H

X

L

H

Entry

H

L

H

X

Clock Suspend or

Active Power Down

Exit

L

H

X

L

H

Entry

H

L

H

X

L

V

Precharge Power Down Mode

Exit

L

H

X

DQM

H

X

V

X

7

L

H

No Operation Command

H

X

H

X

Deep Power Down Entry

H

L

H

L

X

Deep Power Down Exit

L

H

X

8

(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)

Note :

1. OP Code: Operand Code

A0~A10, BA: Program keys. (@MRS, EMRS)

2. MRS can be issued only when all banks are at precharge state.

A new command can be issued after 2 clock cycle of MRS, EMRS.

3. Auto refresh functions is same as CBR refresh of DRAM.

The automatical precharge without Row precharge command is meant by “Auto”.

Auto/Self refresh can be issued only when all banks are at precharge state.

4. BA: Bank select address.

5. During burst read or write with auto precharge, new read/write command cannot be issued.

Another bank read/write command can be issued at every burst length.

6. Bust stop command is valid at every burst length.

7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0)

but masks the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2)

8. After Deep Power Down mode exit, a full new initialization of the memory device is mandatory.

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