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BS616UV2019TIP85 Datasheet(PDF) 4 Page - Brilliance Semiconductor |
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BS616UV2019TIP85 Datasheet(HTML) 4 Page - Brilliance Semiconductor |
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4 / 9 page  Revision 1.1 Jan. 2004 4 R0201-BS616UV2019 JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION (Vcc = 1.9~3.6V) (Vcc = 1.9~3.6V) UNIT t AVAX t RC Read Cycle Time 100 ---- 85 ---- ns t AVQV t AA Address Access Time -- -- 100 -- -- 85 ns t ELQV t ACS1 , 2 Chip Select Access Time (CE,CE2) -- -- 100 -- -- 85 ns t BA t BA Data Byte Control Access Time (LB,UB) ---- 50 ---- 40 ns t GLQV t OE Output Enable to Output Valid -- -- 50 -- -- 40 ns t E1LQX t CLZ Chip Select to Output Low Z (CE,CE2) 15 -- -- 15 -- -- ns t BE t BE Data Byte Control to Output Low Z (LB,UB) 15 ---- 15 ---- ns t GLQX t OLZ Output Enable to Output in Low Z 15 -- -- 15 -- -- ns t EHQZ t CHZ Chip Deselect to Output in High Z (CE,CE2) -- -- 40 -- -- 35 ns t BDO t BDO Data Byte Control to Output High Z (LB,UB) -- -- 40 -- -- 35 ns t GHQZ t OHZ Output Disable to Output in High Z -- -- 35 -- -- 30 ns t AXOX t OH Data Hold from Address Change 15 -- -- 15 -- -- ns AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC ) READ CYCLE ( 48B BGA ignore CE2 condition) AC TEST CONDITIONS (Test Load and Input/Output Reference) KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS MUST BE STEADY MAY CHANGE FROM H TO L DON T CARE: ANY CHANGE PERMITTED DOES NOT APPLY MUST BE STEADY WILL BE CHANGE FROM H TO L CHANGE : STATE UNKNOWN CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE MAY CHANGE FROM L TO H WILL BE CHANGE FROM L TO H , LOW V CC DATA RETENTION WAVEFORM ( CE Controlled ) CE Data Retention Mode Vcc t CDR Vcc t R VIH VIH Vcc VDR 1.0V ≥ CE Vcc - 0.2V ≥ BSI BS616UV2019 (1) 1. tBA is 50ns/40ns (@speed=100ns/85ns) with address toggle. ; tBA is 100ns/85ns (@speed=100ns/85ns) without address toggle. NOTE : MIN. TYP. MAX. MIN. TYP. MAX. Input Pulse Levels Vcc / 0V Input Rise and Fall Times 1V/ns Input and Output Timing Reference Level 0.5Vcc Output Load CL = 100pF+1TTL CL = 30pF+1TTL CYCLE TIME : 100ns CYCLE TIME : 85ns |
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