128M GDDR SDRAM

K4D26323QG-GC

- 5 -

Rev 1.2(Mar. 2005)

INPUT/OUTPUT FUNCTIONAL DESCRIPTION

*1 : The timing reference point for the differential clocking is the cross point of CK and CK.

Symbol

Type

Function

CK, CK*1

Input

The differential system clock Input.

All of the inputs are sampled on the rising edge of the clock except

CKE

Input

Activates the CK signal when high and deactivates the CK signal

when low. By deactivating the clock, CKE low indicates the Power

down mode or Self refresh mode.

CS

Input

CS enables the command decoder when low and disabled the com-

mand decoder when high. When the command decoder is disabled,

new commands are ignored but previous operations continue.

RAS

Input

Latches row addresses on the positive going edge of the CK with

RAS low. Enables row access & precharge.

CAS

Input

Latches column addresses on the positive going edge of the CK with

CAS low. Enables column access.

WE

Input

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

Input/Output

Data input and output are synchronized with both edge of DQS.

Input

Data In mask. Data In is masked by DM Latency=0 when DM is high

Input/Output

Data inputs/Outputs are multiplexed on the same pins.

Input

Selects which bank is to be active.

Input

Row/Column addresses are multiplexed on the same pins.

Power Supply

Power and ground for the input buffers and core logic.

Power Supply

Isolated power supply and ground for the output buffers to provide

improved noise immunity.

Power Supply

Reference voltage for inputs, used for SSTL interface.

NC/RFU

No connection/

Reserved for future use

This pin is recommended to be left "No connection" on the device

MCL

Must Connect Low

Must connect low