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HPC-DEV-IBMC Datasheet(PDF) 8 Page - National Semiconductor (TI) |
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HPC-DEV-IBMC Datasheet(HTML) 8 Page - National Semiconductor (TI) |
8 / 30 page Timing Waveforms (Continued) Serial Decoder Timing Diagram (Mode 2) TLDD10422 – 14 Symbol Parameter Min Max Comments Units TPFS Number of HCK1 Periods between FS Falling Edges 34 TAFS Number of HCK1 Rising Edges during FS Low 1 32 TEFS Hold of FS High after HCK1 Rising Edge 10 Early FS ns TLFS Setup of FS Falling Edge before HCK1 Rising Edge 20 Late FS (Note 8) ns TVFC Delay of TX Output Valid after HCK1 Rising Edge 60 (Note 7) ns THFS Hold of FS Low after HCK1 Rising Edge 20 ns TSFS Setup of FS Rising Edge before HCK1 Rising Edge 20 ns TTTC Delay of TX output TRI-STATE after HCK1 Rising Edge 40 ns TVFR TVFC in Rate Adaptation Mode 75 ns Serial Decoder Timing Diagram (Modes 3 4) TLDD10422 – 15 Symbol Parameter Min Max Comments Units TPFS Number of HCK1 Periods between FS Rising Edges 64 SD Mode 3 TPFS Number of HCK1 Periods between FS Rising Edges 32 SD Mode 4 TAFS Number of HCK1 Falling Edges during FS High 2 62 SD Mode 3 TAFS Number of HCK1 Falling Edges during FS High 2 30 SD Mode 4 TEFS Hold of FS Low after HCK1 Falling Edge 10 Early FS ns TLFS Setup of FS Rising Edge before HCK1 Falling Edge 45 Late FS (Note 8) ns TVFS Delay of TX Output Valid after HCK1 and FS Rising Edges 70 (Note 9) ns THFS Hold of FS High after HCK1 Falling Edge 20 ns TSFS Setup of FS Falling Edge before HCK1 Rising Edge 20 ns TTTC Delay of TX output TRI-STATE after HCK1 Rising Edge 40 ns Note 7 This spec is for 1st bit only Remaining bits are spec’d by transmitter TVTC spec Note 8 Receiver specs TVRS and TVRH are required along with TLFS for receiver operation using serial decoder Note 9 This spec is for 1st bit only and is measured from the later of either FS or HCK1 rising edge Remaining bits are spec’d from HCK1 rising edges by transmitter TVTC spec 8 |
Similar Part No. - HPC-DEV-IBMC |
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Similar Description - HPC-DEV-IBMC |
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