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HPC-DEV-IBMA Datasheet(PDF) 4 Page - National Semiconductor (TI) |
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HPC-DEV-IBMA Datasheet(HTML) 4 Page - National Semiconductor (TI) |
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4 / 30 page  AC Electrical Characteristics (Continued) CPU and DMA Timing (see Notes 1 and 4 and Figures 2 4 6 7 8 and 9 ) VCC e 5V g10% TA e 0 Cto a70 C for HPC46400E b40 Cto a85 C for HPC36400E Symbol Formula Cycle Parameter Min Max Units Note t1ALR CPU Delay of ALE Rising Edge after CKI Rising Edge 0 35 ns (Note 2) DMA Delay of ALE Rising Edge after CKI Falling Edge 0 35 ns (Note 2) t1ALF CPU Delay of ALE Falling Edge after CKI Rising Edge 0 35 ns (Note 2) DMA Delay of ALE Falling Edge after CKI Falling Edge 0 35 ns (Note 2) t2ALR tC a 20 CPU ALE Rising Edge after CK2 Rising Edge 45 ns t2ALF tC a 20 CPU ALE Falling Edge after CK2 Falling Edge 45 ns tLL tC b 9 ALE Pulse Width 41 ns tST tC b 20 Setup of Address Valid before ALE Falling Edge 5 ns (Note 3) tVP tC b 10 CPU Hold of Address Valid after ALE Falling Edge 15 ns tC b 10 DMA 40 ns tARR tC b 20 ALE Falling Edge to RD Falling Edge 30 ns tACC tC a WS b 55 CPU Data Input Valid after Address Output Valid 145 ns tC a WS b 75 DMA 150 ns tRD tC a WS b 35 CPU Data Input Valid after RD Falling Edge 90 ns tC a WS DMA 115 ns tRW tC a WS b 15 CPU RD Pulse Width 110 ns tC a WS b 15 DMA 135 ns tDR tC b 25 Hold of Data Input Valid after RD Rising Edge 0 50 ns tRDA tC b 20 Bus Enable after RD Rising Edge 55 ns tARW tC b 20 ALE Falling Edge to WR Falling Edge 30 ns tWW tCaWS b 15 CPU WR Pulse Width 160 ns tCaWS b 15 DMA 135 ns tV tC a WS b 40 CPU Data Output Valid before WR Rising Edge 110 ns tC a WS b 50 DMA 100 ns tHW tC b 10 Hold of Data Output Valid after WR Rising Edge 15 ns (Note 5) tRDYS RDY Falling Edge before CK2 Rising Edge 45 ns tRDYH RDY Rising Edge after CK2 Rising Edge 0 ns tRDYV WS b tC b 47 CPU RDY Falling Edge after RD or WR Falling Edge 28 ns (Note 6) tC b 47 DMA 53 ns Note 1 These AC characteristics are guaranteed with external clock drive on CKI having 50% duty cycle and with less than 15 pF load on CKO Spec’d tC1R tC1F and CKI duty cycle limits are not tested but are guaranteed functional by design Keep in mind that when SLOW mode is selected fC (Operating Frequency) will be the external frequency divided by 4 and that value should be used in all formulas relating to the AC Characteristics Note 2 Do not design with this parameter unless CKI is driven with an active signal meeting TC1R and TC1F specs When using a passive crystal circuit its stability is not guaranteed if either CKI or CKO is connected to any external logic other than the passive components of the crystal circuit Note 3 Setup of HBE valid before ALE falling edge is 0 ns minimum Setup of BS0 thru BS3 valid before ALE falling edge when in extended addressing mode is 0 ns minimum Note 4 WS (tWAIT) c (number of preprogrammed wait states) Minimum and maximum values are calculated at maximum operating frequency fC e 20 MHz with one wait state preprogrammed These values are guaranteed with AC loading of 100 pF on Port A 50 pF on CK2 80 pF on other outputs and DC loading of the pin’s DC spec non CMOS IOL or IOH Note 5 Hold of HBE Output Valid after WR rising edge is 0 ns minimum Hold of BS0 thru BS3 Output Valid after WR rising edge when in extended addressing mode is 0 ns minimum Note 6 In HPC in-circuit emulators the tRDYV formulas are WS b tC b 57 and tC b 57 yielding minimums of 18 ns and 43 ns for CPU and DMA cycles respectively 4 |
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