INDUSTRIALTEMPERATURERANGE

IDT74ALVCH162374

3.3VCMOS16-BITEDGE-TRIGGEREDD-TYPEFLIP-FLOP

1

MARCH 1999

INDUSTRIAL TEMPERATURE RANGE

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

© 1999 Integrated Device Technology, Inc.

DSC-4565/4

FEATURES:

• 0.5 MICRON CMOS Technology

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

machine model (C = 200pF, R = 0)

• CMOS power levels (0.4

μμμμμ W typ. static)

• Rail-to-Rail output swing for increased noise margin

• Available in TSSOP package

FUNCTIONAL BLOCK DIAGRAM

DESCRIPTION:

This 16-bit edge-triggered D-type flip-flop is built using advanced dual metal

CMOStechnology.TheALVCH162374isparticularlysuitableforimplementing

bufferregisters,I/Oports,bidirectionalbusdrivers,andworkingregisters.Itcan

be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of

the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up

atthedata(D)inputs.

OEcanbeusedtoplacetheeightoutputsineitheranormal

logic state (high or low logic levels) or a high-impedance state. In the high-

impedance state, the outputs neither load nor drive the bus lines significantly.

The high-impedance state and the increased drive provide the capability to

drive bus lines without need for interface or pullup components.

OE does not

affect internal operations of the flip-flop. Old data can be retained or new data

can be entered while the outputs are in the high-impedance state.

TheALVCH162374hasseriesresistorsinthedeviceoutputstructurewhich

will significantly reduce line noise when used with light loads. This driver has

been designed to drive ±12mA at the designated threshold levels.

The ALVCH162374 has “bus-hold” which retains the inputs’ last state

whenevertheinputgoestoahighimpedance.Thispreventsfloatinginputsand

eliminates the need for pull-up/down resistor.

DRIVE FEATURES:

• Balanced Output Drivers: ±12mA

• Low switching noise

IDT74ALVCH162374

3.3V CMOS 16-BIT EDGE-

TRIGGERED D-TYPE FLIP-

FLOP WITH 3-STATE OUTPUTS

AND BUS-HOLD

1

OE

C1

1D

1

47

1

CLK

1

TO 7 OTHER CHANNELS

2

OE

2

36

2

CLK

2

TO 7 OTHER CHANNELS

1

48

2

24

25

13

C1

1D

APPLICATIONS:

• 3.3V high speed systems

• 3.3V and lower voltage computing systems