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5 page 
5 CAT5419 Document No. 2115, Rev. F WRITE CYCLE LIMITS Over recommended operating conditions unless otherwise stated. Symbol Parameter Min Typ Max Units tWR Write Cycle Time 5 ms The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address. tHIGH SCL SDA IN SDA OUT tLOW tF tLOW tR tBUF tSU:STO tSU:DAT tHD:DAT tHD:STA tSU:STA tAA tDH Figure 1. Bus Timing tWR STOP CONDITION START CONDITION ADDRESS ACK 8TH BIT BYTE n SCL SDA Figure 2. Write Cycle Timing START BIT SDA STOP BIT SCL Figure 3. Start/Stop Timing RELIABILITY CHARACTERISTICS Over recommended operating conditions unless otherwise stated. Symbol Parameter Reference Test Method Min Typ Max Units NEND(1) Endurance MIL-STD-883, Test Method 1033 1,000,000 Cycles/Byte TDR(1) Data Retention MIL-STD-883, Test Method 1008 100 Years VZAP(1) ESD Susceptibility MIL-STD-883, Test Method 3015 2000 Volts ILTH(1)(2) Latch-Up JEDEC Standard 17 100 mA Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. |
