MB86291A

8

•••• Video Capture Interface

Note : The video capture interface inputs digital video signals in the ITU-RBT-656 format.

•••• Clock Input

*1 : Do not connect anything.

*2 : Input the “H” level.

Notes :

• The clock input block inputs the clock signal that serves as the basis for the reference clock for the internal

operating clock and display dot clock. Usually input 4 Fsc (

= 14.31818 MHz) . The internal PLL generates

the internal operating clock signal of 100 MHz and the display reference clock signal of 200 MHz.

• The internal operating clock signal to be used can be selected between the clock signal (100 MHz)

generated by the internal PLL and the bus clock BCLKI input to the host CPU interface. Select the BCLKI

input to use the host CPU bus at 100 MHz.

Note : Use the CLKSEL pin to select the input clock frequency for using the internal PLL with CKM

= L.

Note : Immediately after turning the power supply on, input a pulse whose low level period is 500 ns or more to the

S pin before setting it to high level. After the S signal goes high, input the RESET signal at low level for 300

µs or more

Pin Name

Input/output

Function

CCLK

Input

Digital video input clock signal input

VI0-VI7

Input

Digital video data input

Pin Name

Input/output

Function

CLK

Input

Clock input signal

S

Input

PLL reset signal

CKM

Input

Clock mode signal

CLKSEL1, CLKSEL0

Input

Clock rate select signal

Input/output

For connection of crystal oscillator (Reserved)

Input

For selection of crystal oscillator (Reserved)

CKM

Clock Mode

L

Select internal PLL output.

H

Select host CPU bus clock (BCLKI)

CLKSEL1

CLKSEL0

Clock Frequency

L

L

Input 13.5 MHz.

L

H

Input 14.32 MHz.

H

L

Input 17.73 MHz.

HH

Reserved