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DS80C411-FNY Datasheet(PDF) 5 Page - Dallas Semiconductor

Part # DS80C411-FNY
Description  Network Microcontrollers with Ethernet and CAN
Download  102 Pages
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Manufacturer  DALLAS [Dallas Semiconductor]
Direct Link  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS80C411-FNY Datasheet(HTML) 5 Page - Dallas Semiconductor

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DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN
5 of 102
EXTERNAL CLOCK OSCILLATOR (XTAL1) CHARACTERISTICS
PARAMETER
SYMBOL
MIN
MAX
UNITS
Clock Oscillator Period
tCLK
See External Clock
Oscillator Frequency
Clock Symmetry at 0.5 x VCC3
tCH
0.45 tCLK
0.55 tCLK
ns
Clock Rise Time
tCR
3
ns
Clock Fall Time
tCF
3
ns
EXTERNAL CLOCK DRIVE
SYSTEM CLOCK TIME PERIODS (tCLCL, tCHCL, tCLCH)
SYSTEM CLOCK SELECTION
SYSTEM CLOCK HIGH (tCHCL ) AND
SYSTEM CLOCK LOW (tCLCH)
4X/
2X
CD1
CD0
SYSTEM CLOCK
PERIOD tCLCL
MIN
MAX
1
0
0
tCLK / 4
0.45 (tCLK / 4)
0.55 (tCLK / 4)
0
0
0
tCLK / 2
0.45 (tCLK / 2)
0.55 (tCLK / 2)
X
1
0
tCLK
0.45 tCLK
0.55 tCLK
X
1
1
256 tCLK
0.45 (256 tCLK)
0.55 (256 tCLK)
Note 1: Figure 21 shows a detailed description and illustration of the system clock selection.
Note 2: When an external clock oscillator is used in conjunction with the default system clock selection (CD1:CD0 = 10b), the
minimum/maximum system clock high (tCHCL) and system clock low (tCLCH) periods are directly related to clock oscillator duty cycle.
MOVX CHARACTERISTICS (MULTIPLEXED ADDRESS/DATA BUS) (Note 1)
(VCC3 = 3.0V to 3.6V, VCC1 = 1.8V ±10%, TA = -40
°C to +85°C.)
PARAMETER
SYMBOL
MIN
MAX
UNITS
STRETCH VALUES
CST (MD2:0)
tCLCL + tCHCL - 5
CST = 0
2tCLCL - 5
1
£ CST £ 3
MOVX ALE Pulse Width
tLHLL2
6tCLCL - 5
ns
4
£ CST £ 7
tCHCL - 5
CST = 0
tCLCL - 6
1
£ CST £ 3
Port 0 MOVX Address Valid
to ALE Low
tAVLL2
5tCLCL - 6
ns
4
£ CST £ 7
tCLCH - 2
CST = 0
tCLCL - 2
1
£ CST £3
Port 0 MOVX Address Hold
after ALE Low
tLLAX2
and tLLAX3
5tCLCL - 2
ns
4
£ CST £ 7
2tCLCL - 5
CST = 0
RD Pulse Width (P3.7 or
PSEN)
tRLRH
(4 x CST) tCLCL - 3
ns
1
£ CST £ 7
2tCLCL - 5
CST = 0
WR Pulse Width (P3.6)
tWLWH
(4 x CST) tCLCL - 3
ns
1
£ CST £ 7
2tCLCL - 18
CST = 0
RD (P3.7 or PSEN) Low to
Valid Data In
tRLDV
(4 x CST) tCLCL - 18
ns
1
£ CST £ 7
Data Hold After
RD (P3.7 or
PSEN) High
tRHDX
-2
ns
tCR
tCF
tCLK
tCH
XTAL1
tCL


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