9

4318C–ULC–08/05

ATU18

Atmel Flow

With 0.18um technology, ATMEL has introduced Physical synthesis to optimize design

speed. Physical synthesis takes into account the placement and the routing of the cells, and the

optimization in incremental mode can be done on the full design or only partially. The result is

that ATMEL has faster chips, using the same RTL code. Less iterations are necessary and the

timings target is quickly reached.

Code

SYNTHESIS

Placement

Clock Tree

synthesis

Route

ATMEL Bonding

diagram

Customer Timing

constraints

Post layout Simulations,

Timing & power Analysis

Timing , Power OPT

Customer RTL

DRC - LVS

TAPE OUT

SCAN, JTAG,

BIST

NETLIST for

Layout

ATMEL

NETLIST

Formal Proof

Customer Pinout