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MT88L70AN Datasheet(PDF) 6 Page - Zarlink Semiconductor Inc |
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MT88L70AN Datasheet(HTML) 6 Page - Zarlink Semiconductor Inc |
6 / 16 page MT88L70 Data Sheet 6 Zarlink Semiconductor Inc. Differential Input Configuration The input arrangement of the MT88L70 provides a differential-input operational amplifier as well as a bias source (VRef) which is used to bias the inputs at mid-rail. Provision is made for connection of a feedback resistor to the op- amp output (GS) for adjustment of gain. In a single-ended configuration, the input pins are connected as shown in Figure 6 with the op-amp connected for unity gain and VRef biasing the input at 1/2VDD. Figure 5 shows the differential configuration, which permits the adjustment of gain with the feedback resistor R5. Figure 5 - Differential Input Configuration Crystal Oscillator The internal clock circuit is completed with the addition of an external 3.579545 MHz crystal and is connected as shown in Figure 6 (Single-ended Input Configuration). C1 R1 C2 R4 IN+ IN- R5 R2 R3 GS VRef + - MT88L70 DIFFERNTIAL INPUT AMPLIFIER C1 = C2 = 10 nF R1 = R4 = R5 = 100 kΩ R2 = 60 kΩ, R3, = 37.5 kΩ R3 = R2R5 R2 + R5 VOLTAGE GAIN (AV diff) = R5 R1 INPUT IMPEDANCE (ZINDIFF) = 2 R12 + 1 ωC 2 All resistors are ± 1% tolerance. All capacitors are ± 5% tolerance. |
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Similar Description - MT88L70AN |
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