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UPD44324362F5-E37-EQ2 Datasheet(PDF) 10 Page - NEC |
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UPD44324362F5-E37-EQ2 Datasheet(HTML) 10 Page - NEC |
10 / 40 page 10 Data Sheet M16780EJ3V0DS µPD44324082, 44324092, 44324182, 44324362 Power-on Sequence The following two timing charts show the recommended power-on sequence, i.e., when starting the clock after VDD/VDDQ stable and when starting the clock before VDD/VDDQ stable. 1. Clock starts after VDD/VDDQ stable The clock is supplied from a controller. (a) VDD/VDDQ VDD/VDDQ Stable (< ±0.1 V DC per 50 ns) DLL# Clock Start Normal Operation Start Clock Fix high (or tied to VDDQ) 20 ns (MIN.) 1,024 cycles or more Stable Clock Note Note Input a stable clock from the start. (b) VDD/VDDQ DLL# Switched to high after Clock is stable. Unstable Clock (level, frequency) VDD/VDDQ Stable (< ±0.1 V DC per 50 ns) Clock Clock Start Normal Operation Start 1,024 cycles or more Stable Clock (c) VDD/VDDQ DLL# 30 ns. (MIN.) Clock Stop VDD/VDDQ Stable (< ±0.1 V DC per 50 ns) Fix high (or tied to VDDQ) Unstable Clock (level, frequency) Clock Clock Start Normal Operation Start 1,024 cycles or more Stable Clock |
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