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UPD44165362F5-E75-EQ1 Datasheet(PDF) 6 Page - NEC |
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UPD44165362F5-E75-EQ1 Datasheet(HTML) 6 Page - NEC |
6 / 32 page 6 Data Sheet M15824EJ7V 1DS µµµµPD44165082, 44165182, 44165362 Pin Identification Symbol Description A Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of K for READ cycles and must meet the setup and hold times around the rising edge of /K for WRITE cycles. Balls 9A, 3A, 10A, and 2A are reserved for the next higher-order address inputs on future devices. All transactions operate on a burst of two words (one clock period of bus activity). These inputs are ignored when device is deselected. D0 to Dxx Synchronous Data Inputs: Input data must meet setup and hold times around the rising edges of K and /K during WRITE operations. See Pin Configurations for ball site location of individual signals. x8 device uses D0 to D7. x18 device uses D0 to D17. x36 device uses D0 to D35. Q0 to Qxx Synchronous Data Outputs: Output data is synchronized to the respective C and /C or to K and /K rising edges if C and /C are tied HIGH. This bus operates in response to /R commands. See Pin Configurations for ball site location of individual signals. x8 device uses Q0 to Q7. x18 device uses Q0 to Q17. x36 device uses Q0 to Q35. /R Synchronous Read: When LOW this input causes the address inputs to be registered and a READ cycle to be initiated. This input must meet setup and hold times around the rising edge of K. /W Synchronous Write: When LOW this input causes the address inputs to be registered and a WRITE cycle to be initiated. This input must meet setup and hold times around the rising edge of K. /BWx /NWx Synchronous Byte Writes (Nibble Writes on x8): When LOW these inputs cause their respective byte or nibble to be registered and written during WRITE cycles. These signals must meet setup and hold times around the rising edges of K and /K for each of the two rising edges comprising the WRITE cycle. See Pin Configurations for signal to data relationships. K, /K Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data on the rising edge of K and the rising edge of /K. /K is ideally 180 degrees out of phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges. C, /C Output Clock: This clock pair provides a user controlled means of tuning device output data. The rising edge of /C is used as the output timing reference for first output data. The rising edge of C is used as the output reference for second output data. Ideally, /C is 180 degrees out of phase with C. C and /C may be tied HIGH to force the use of K and /K as the output reference clocks instead of having to provide C and /C clocks. If tied HIGH, C and /C must remain HIGH and not be toggled during device operation. CQ, /CQ Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. These signals run freely and do not stop when Q tristates. ZQ Output Impedance Matching Input: This input is used to tune the device outputs to the system data bus impedance. DQ and CQ output impedance are set to 0.2 x RQ, where RQ is a resistor from this bump to ground. This pin cannot be connected directly to GND or left unconnected. Also, in this product, there is no function to minimize the output impedance by connecting ZQ directly to VDDQ. /DLL DLL Disable: When LOW, this input causes the DLL to be bypassed for stable low frequency operation. TMS TDI IEEE 1149.1 Test Inputs: 1.8V I/O levels. These balls may be left Not Connected if the JTAG function is not used in the circuit. TCK IEEE 1149.1 Clock Input: 1.8V I/O levels. This pin must be tied to VSS if the JTAG function is not used in the circuit. TDO IEEE 1149.1 Test Output: 1.8V I/O level. VREF HSTL Input Reference Voltage: Nominally VDDQ/2. Provides a reference voltage for the input buffers. VDD Power Supply: 1.8V nominal. See DC Characteristics and Operating Conditions for range. VDDQ Power Supply: Isolated Output Buffer Supply. Nominally 1.5V. 1.8V is also permissible. See DC Characteristics and Operating Conditions for range. VSS Power Supply: Ground NC No Connect: These signals are internally connected and appear in the JTAG scan chain as the logic level applied to the ball sites. These signals may be connected to ground to improve package heat dissipation. |
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