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UPD44165182F5-E75-EQ1 Datasheet(PDF) 8 Page - NEC |
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UPD44165182F5-E75-EQ1 Datasheet(HTML) 8 Page - NEC |
8 / 32 page 8 Data Sheet M15824EJ7V 1DS µµµµPD44165082, 44165182, 44165362 Truth Table Operation CLK /R /W D or Q WRITE cycle L → H X L Data in Load address, input write data on Input data DA (A+0) DA (A+1) consecutive K and /K rising edge Input clock K( t ) ↑ /K( t ) ↑ READ cycle L → H L X Data out Load address, output data on Output data QA (A+0) QA (A+1) consecutive C and /C rising edge Output clock /C(t+1) ↑ C(t+2) ↑ NOP (No operation) L → H H H D=X or Q=High-Z STANDBY(Clock stopped) Stopped X X Previous state Remarks 1. H : High level, L : Low level, × : don’t care, ↑ : rising edge. 2. Data inputs are registered at K and /K rising edges. Data outputs are delivered at C and /C rising edges except if C and /C are HIGH then Data outputs are delivered at K and /K rising edges. 3. All control inputs in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of K. All control inputs are registered during the rising edge of K. 4. This device contains circuitry that will ensure the outputs will be in high impedance during power-up. 5. Refer to state diagram and timing diagrams for clarification. 6. It is recommended that K = /(/K) = C = /(/C) when clock is stopped. This is not essential but permits most rapid restart by overcoming transmission line charging symmetrically. |
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