8

Data Sheet M15824EJ7V

1DS

Truth Table

Operation

CLK

/R

/W

D or Q

WRITE cycle

L

→ H

X

L

Data in

Load address, input write data on

Input data

consecutive K and /K rising edge

Input clock

K( t )

↑

/K( t )

↑

READ cycle

L

→ H

L

X

Data out

Load address, output data on

Output data

consecutive C and /C rising edge

Output clock

/C(t+1)

↑

C(t+2)

↑

NOP (No operation)

L

→ H

H

H

D=X or Q=High-Z

STANDBY(Clock stopped)

Stopped

X

X

Previous state

Remarks 1. H : High level, L : Low level,

× : don’t care, ↑ : rising edge.

2. Data inputs are registered at K and /K rising edges. Data outputs are delivered at C and /C rising edges

except if C and /C are HIGH then Data outputs are delivered at K and /K rising edges.

3. All control inputs in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of

K. All control inputs are registered during the rising edge of K.

4. This device contains circuitry that will ensure the outputs will be in high impedance during power-up.

5. Refer to state diagram and timing diagrams for clarification.

6. It is recommended that K = /(/K) = C = /(/C) when clock is stopped. This is not essential but permits most

rapid restart by overcoming transmission line charging symmetrically.