10

Data Sheet M15822EJ7V

1DS

Bus Cycle State Diagram

READ DOUBLE

Count = Count + 2

WRITE DOUBLE

Count = Count + 2

Power UP

Write

NOP

Supply voltage provided

LOAD NEW

ADDRESS

Count = 0

NOP

ADVANCE ADDRESS

BY TWO

ADVANCE ADDRESS

BY TWO

Load, Count = 4

Read

Load, Count = 4

Always

Count = 2

Always

Count = 2

Load

NOP,

Count = 4

NOP,

Count = 4

Remarks 1. A0 and A1 are internally advanced in accordance with the burst order table.

Bus cycle is terminated after burst count = 4.

2. State transitions: L = (/LD = LOW); /L = (/LD = HIGH); R = (/R, W = HIGH); W = (/R, W = LOW).

3. State machine control timing sequence is controlled by K.