11

Data Sheet M15561EJ3V0DS

µPD4481161, 4481181, 4481321, 4481361

Asynchronous Truth Table

Operation

/G

I/O

Read Cycle

L

Dout

Read Cycle

H

High-Z

Write Cycle

×

High-Z, Din

Deselected

×

High-Z

Remark

× : don’t care

Synchronous Truth Table

Operation

/CE

CE2

/CE2

ADV

/WE

/BWs

/CKE

CLK

I/O

Address

Note

Deselected

H

××

L

××

LL

→ H

High-Z

None

1

Deselected

×

L

×

L

××

LL

→ H

High-Z

None

1

Deselected

××

HL

××

LL

→ H

High-Z

None

1

Continue Deselected

××

×

H

××

LL

→ H

High-Z

None

1

Read Cycle / Begin Burst

L

H

L

L

H

×

LL

→ H

Dout

External

Read Cycle / Continue Burst

××

×

H

××

LL

→ H

Dout

Next

Write Cycle / Begin Burst

L

H

LLLL

L

L

→ H

Din

External

Write Cycle / Continue Burst

××

×

H

×

LL

L

→ HDin

Next

Write Cycle / Write Abort

L

H

L

L

L

H

L

L

→ H

High-Z

External

Write Cycle / Write Abort

××

×

H

×

HL

L

→ H

High-Z

Next

Stall / Ignore Clock Edge

××

××××

HL

→ H

−

Current

2

Notes

1. Deselect status is held until new “Begin Burst” entry.

2. If an Ignore Clock Edge command occurs during a read operation, the I/O bus will remain active (low

impedance). If it occurs during a write cycle, the bus will remain high impedance. No write operation will

be performed during the Ignore Clock Edge cycle.

Remarks 1.

× : don’t care

2. /BWs = L means any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) are LOW.

/BWs = H means all byte write enables (/BW1, /BW2, /BW3 or /BW4) are HIGH.