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UPD4616112F9-BC90-BC2 Datasheet(PDF) 10 Page - NEC |
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UPD4616112F9-BC90-BC2 Datasheet(HTML) 10 Page - NEC |
10 / 32 page Data Sheet M15085EJ5V0DS 10 µµµµPD4616112 5 5 5 5 Read Cycle (BC version) Parameter Symbol µPD4616112-BC80 µPD4616112-BC90 Unit Notes MIN. MAX. MIN. MAX. Read cycle time tRC 80 10,000 90 10,000 ns 1 Identical address read cycle time tRC1 80 10,000 90 10,000 ns 2 Address skew time tSKEW 10 20 ns 3 /CS pulse width tCP 10 10 ns Address access time tAA 80 90 ns 4 /CS access time tACS 80 90 ns /OE to output valid tOE 35 40 ns 5 /LB, /UB to output valid tBA 35 40 ns Output hold from address change tOH 10 10 ns /CS to output in low impedance tCLZ 10 10 ns /OE to output in low impedance tOLZ 55 ns /LB, /UB to output in low impedance tBLZ 55 ns /CS to output in high impedance tCHZ 25 25 ns /OE to output in high impedance tOHZ 25 25 ns /LB, /UB to output in high impedance tBHZ 25 25 ns Notes 1. One read cycle (tRC) must satisfy the minimum value (tRC(MIN.)) and maximum value (tRC(MAX.) = 10 µs). tRC indicates the time from the /CS low level input point or address change start point, whichever is later, to the /CS high level input point or the next address change start point, whichever is earlier. As a result, there are the following four conditions for tRC. 1) Time from address change start point to /CS high level input point (address access) 2) Time from address change start point to next address change start point (address access) 3) Time from /CS low level input point to next address change start point (/CS access) 4) Time from /CS low level input point to /CS high level input point (/CS access) 2. The identical address read cycle time (tRC1) is the cycle time of one read operation when performing continuous read operations toggling /OE , /LB, and /UB with the address fixed and /CS low level. Perform settings so that the sum (tRC) of the identical address read cycle times (tRC1) is 10 µs or less. 3. tSKEW indicates the following three types of time depending on the condition. 1) When switching /CS from high level to low level, tSKEW is the time from the /CS low level input point until the next address is determined. 2) When switching /CS from low level to high level, tSKEW is the time from the address change start point to the /CS high level input point. 3) When /CS is fixed to low level, tSKEW is the time from the address change start point until the next address is determined. Since specs are defined for tSKEW only when /CS is active, tSKEW is not subject to limitations when /CS is switched from high level to low level following address determination, or when the address is changed after /CS is switched from low level to high level. 4. Regarding tAA and tACS, only tAA is satisfied during address access (refer to 1) and 2) of Note 1), and only tACS is satisfied during /CS access (refer to 3) of Note 1). 5. Regarding tBA and tOE, only tBA is satisfied if /OE becomes active later than /UB and /LB, and only tOE is satisfied if /UB and /LB become active before /OE. |
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