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MOS INTEGRATED CIRCUIT

8M-BIT CMOS SYNCHRONOUS FAST SRAM

FLOW THROUGH OPERATION

Document No. M14521EJ3V0DS00 (3rd edition)

Date Published December 2002 NS CP(K)

Printed in Japan

DATA SHEET

The mark

shows major revised points.

2000

Description

The

µPD4482161 is a 524,288-word by 16-bit, the µPD4482181 is a 524,288-word by 18-bit, the µPD4482321 is a

262,144-word by 32-bit and the

µPD4482361 is a 262,144-word by 36-bit synchronous static RAM fabricated with

advanced CMOS technology using Full-CMOS six-transistor memory cell.

The

µPD4482161, µPD4482181, µPD4482321 and µPD4482361 integrate unique synchronous peripheral circuitry, 2-bit

burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single

clock input (CLK).

The

µPD4482161, µPD4482181, µPD4482321 and µPD4482361 are suitable for applications which require synchronous

operation, high speed, low voltage, high density and wide bit configuration, such as cache and buffer memory.

ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”). In

the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal operation.

The

µPD4482161, µPD4482181, µPD4482321 and µPD4482361 are packaged in 100-pin PLASTIC LQFP with a 1.4

mm package thickness for high density and low capacitive loading.

Features

• 3.3 V or 2.5 V core supply

• Synchronous operation

−40 to +85 °C (-A65Y, -A75Y, -A85Y, -C75Y, -C85Y)

• Internally self-timed write control

• Burst read / write : Interleaved burst and linear burst sequence

• Fully registered inputs for flow through operation

• All registers triggered off positive clock edge

• 3.3 V or 2.5 V LVTTL Compatible : All inputs and outputs

• Fast clock access time : 6.5 ns (133 MHz), 7.5 ns (117 MHz), 8.5 ns (100 MHz)

• Asynchronous output enable : /G

• Burst sequence selectable : MODE

• Sleep mode : ZZ (ZZ = Open or Low : Normal operation)

• Separate byte write enable : /BW1 to /BW4, /BWE (

µPD4482321, µPD4482361)

/BW1, /BW2, /BWE (

µPD4482161, µPD4482181)

Global write enable : /GW

• Three chip enables for easy depth expansion

• Common I/O using three state outputs