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UPD4481321GF-A65 Datasheet(PDF) 9 Page - NEC

Part # UPD4481321GF-A65
Description  8M-BIT ZEROSB SRAM FLOW THROUGH OPERATION
Download  28 Pages
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

UPD4481321GF-A65 Datasheet(HTML) 9 Page - NEC

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Data Sheet M15561EJ3V0DS
µPD4481161, 4481181, 4481321, 4481361
[
µµµµPD4481321, µµµµPD4481361]
A0 to A17
MODE
CLK
/CKE
ADV
/BW1
/BW2
/WE
/G
/CE
CE2
/CE2
Address
register 0
Burst
logic
Write address
register
Write registry and
data coherency
control logic
Write
drivers
ADV
K
A1
A0
A1’
A0’
Read
logic
Input
register E
E
I/O1 to I/O32
I/OP1 to I/OP4
18
16
18
18
18
32/36
32/36
32/36
32/36
/BW3
/BW4
ZZ
Power down control
K
Memory Cell Array
256 x 32 columns
(8,388,608 bits)
256 x 36 columns
(9,437,184 bits)
1,024 rows
[
µµµµPD4481321, µµµµPD4481361]
Interleaved Burst Sequence Table (MODE = VDD)
External Address
A17 to A2, A1, A0
1st Burst Address
A17 to A2, A1, /A0
2nd Burst Address
A17 to A2, /A1, A0
3rd Burst Address
A17 to A2, /A1, /A0
Linear Burst Sequence Table (MODE = VSS)
External Address
A17 to A2, 0, 0
A17 to A2, 0, 1
A17 to A2, 1, 0
A17 to A2, 1, 1
1st Burst Address
A17 to A2, 0, 1
A17 to A2, 1, 0
A17 to A2, 1, 1
A17 to A2, 0, 0
2nd Burst Address
A17 to A2, 1, 0
A17 to A2, 1, 1
A17 to A2, 0, 0
A17 to A2, 0, 1
3rd Burst Address
A17 to A2, 1, 1
A17 to A2, 0, 0
A17 to A2, 0, 1
A17 to A2, 1, 0


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