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UPD4482161GF-A85 Datasheet(PDF) 9 Page - NEC

Part # UPD4482161GF-A85
Description  8M-BIT CMOS SYNCHRONOUS FAST SRAM FLOW THROUGH OPERATION
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

UPD4482161GF-A85 Datasheet(HTML) 9 Page - NEC

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9
µPD4482161, 4482181, 4482321, 4482361
Data Sheet M14521EJ3V0DS
[
µµµµPD4482321, µµµµPD4482361]
Address
register
Binary
counter
and logic
CLR
Q0
Q1
Byte 1
Write register
Byte 1
Write driver
8/9
Byte 2
Write register
Byte 2
Write driver
8/9
Byte 3
Write register
Byte 3
Write driver
8/9
Byte 4
Write register
Byte 4
Write driver
8/9
Enable
register
Row and column
Input
register
Output
buffer
32/36
18
18
16
18
A0, A1
A1’
A0’
32/36
4
32/36
A0 to A17
MODE
/ADV
CLK
/AC
/AP
/BW1
/BW2
/BW3
/BW4
/BWE
/GW
/CE
CE2
/CE2
/G
I/O1 to I/O32
I/OP1 to I/OP4
ZZ
Power down control
Memory cell array
1,024 rows
256
× 32 columns
(8,388,608 bits)
256
× 36 columns
(9,437,184 bits)
decoders
Burst Sequence
[
µµµµPD4482321, µµµµPD4482361]
Interleaved Burst Sequence Table (MODE = VDD)
External Address
A17 to A2, A1, A0
1st Burst Address
A17 to A2, A1, /A0
2nd Burst Address
A17 to A2, /A1, A0
3rd Burst Address
A17 to A2, /A1, /A0
Linear Burst Sequence Table (MODE = VSS)
External Address
A17 to A2, 0, 0
A17 to A2, 0, 1
A17 to A2, 1, 0
A17 to A2, 1, 1
1st Burst Address
A17 to A2, 0, 1
A17 to A2, 1, 0
A17 to A2, 1, 1
A17 to A2, 0, 0
2nd Burst Address
A17 to A2, 1, 0
A17 to A2, 1, 1
A17 to A2, 0, 0
A17 to A2, 0, 1
3rd Burst Address
A17 to A2, 1, 1
A17 to A2, 0, 0
A17 to A2, 0, 1
A17 to A2, 1, 0


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