Data Sheet M14081EJ5V0DS

8

µµµµPD4416016

Write Cycle Timing Chart 2 (/CS Controlled)

Data input

High impedance

Address (Input)

/CS (Input)

/LB, /UB (Input)

I/O (Input)

High impedance

/WE (Input)

Cautions 1. /CS or /WE should be fixed to high level during address transition.

2. Do not input data to the I/O pins while they are in the output state.

Remark

Write operation is done during the overlap time of a low level /CS and a low level /WE and a low level /LB

(or low level /UB).

Write Cycle Timing Chart 3 (/LB, /UB Controlled)

Data input

High impedance

Address (Input)

/LB, /UB (Input)

I/O (Input)

High impedance

/WE (Input)

/CS (Input)

Cautions 1. /CS or /WE should be fixed to high level during address transition.

2. Do not input data to the I/O pins while they are in the output state.

Remark

Write operation is done during the overlap time of a low level /CS and a low level /WE and a low level /LB

(or low level /UB).

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