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UPD444016-Y Datasheet(PDF) 10 Page - NEC |
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UPD444016-Y Datasheet(HTML) 10 Page - NEC |
10 / 16 page 10 µµµµPD444016-Y Preliminary Data Sheet M15391EJ1V0DS Write Cycle Timing Chart 2 (/CS Controlled) tWC tAS tCW tAW tWP tWR tDW tDH Address (Input) /CS (Input) /WE (Input) /LB, /UB (Input) High impedance Data in High impedance tBW I/O (Input) Cautions 1. /CS or /WE should be fixed to high level during address transition. 2. Do not input data to the I/O pins while they are in the output state. Remark Write operation is done during the overlap time of a low level /CS, /LB and/or /UB, and a low level /WE. |
Similar Part No. - UPD444016-Y |
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Similar Description - UPD444016-Y |
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