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L8115 Datasheet(PDF) 9 Page - Unisonic Technologies |
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L8115 Datasheet(HTML) 9 Page - Unisonic Technologies |
9 / 13 page UTC L8115 LINEAR INTEGRATED CIRCUIT UTC UNISONIC TECHNOLOGIES CO., LTD. 9 QW-R123-005,B APPLICATIONS CIRCUIT The diagrams below show partial application circuits for the UTC series showing all external components required for appropriate biasing. The bias circuits are unconditionally stable over the full temperature range with the associated FETs and gate and drain capacitors in circuit. Capacitors C2 and C4 ensure that residual power supply and substrate generator noise is not allowed to affect other external circuits which may be sensitive to RF interference. They also serve to suppress any potential RF feedthrough between stages via the UTC device. These capacitors are required for all stages used. Values of 10nF and 4.7nF respectively are recommended however this is design dependent and any value between 1nF and 100nF could be used. The capacitors CNB and CSUB are an integral part of the UTCs negative supply generator. The negative bias voltage is generated on-chip using an internal oscillator. The required value of capacitors CNB and CSUB is 47nF. This generator produces a low current supply of approximately -3 volts. Although this generator is intended purely to bias the external FETs, it can be used to power other external circuits via the CSUB pin. Resistor RCAL sets the drain current at which all external FETs are operated. If any bias control circuit is not required, its related drain and gate connections may be left open circuit without affecting the operation of the remaining bias circuits. The UTC L8115 has been designed to protect the external FETs from adverse operating conditions. With a JFET connected to any bias circuit, the gate output voltage of the bias circuit can not exceed the range -3V to 1V under any conditions, including powerup and powerdown transients. All the bias stages include drain currents limits which work independently in each stage. Should the negative bias generator be shorted or overloaded so that the drain current of the external FETs can no longer be controlled, the drain supply to FETs is shut down to avoid damage to the FETs by excessive drain current. * Stripline Elements * C1 * L2 * C3 C4 10nF Q1 *L1 C2 10nF CNB 47nF CSUB 47nF R1 4.7nF LNB Downfeed R2 2k Rcal Fin Lov Csub HB LB G1 D12 C1 G2 G3 D3 Gnd Cnb1 Cnb2 Vpol Vcc UTC L8115 SSOP16 (150mil) Vcc * L3 * C5 C6 10nF SSOP16(150mil) Applications circuit Q2 1 33k |
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