Philips Semiconductors

NE56610/11/12 Series

System Reset

February 23, 2001

7 of 9

document number here

TIMING DIAGRAM

The Timing Diagram shown in Figure 15 depicts the operation

of the device. Letters indicate events on the Time axis.

rise. Also the Reset voltage initially rises but then abruptly

(approximately 0.8V) that activates the internal bias circuitry.

normal.

In a microprocessor based system these events remove the

reset from the microprocessor, allowing it to function normally.

Reset goes low).

increasing.

goes high.

from the logic device is applied at the M/R pin. With the falling

edge of the manual reset signal, the "H" transport delay time

elapsed and the Vout reset goes high.

reset goes low.

where normal internal circuit bias is no longer able to maintain a

decreases to zero.

AB

C

G

H

JK

BC

D

E

FH

L

K

L

M/R

TIME

V

V

V

Figure 15. Timing Diagram