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UPD23C64080JLGY-XXX-MJH Datasheet(PDF) 10 Page - NEC

Part # UPD23C64080JLGY-XXX-MJH
Description  64M-BIT MASK-PROGRAMMABLE ROM 8M-WORD BY 8-BIT (BYTE MODE) / 4M-WORD BY 16-BIT (WORD MODE) PAGE ACCESS MODE
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

UPD23C64080JLGY-XXX-MJH Datasheet(HTML) 10 Page - NEC

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Data Sheet M16065EJ3V0DS
10
µPD23C64040JL, 23C64080JL
AC Characteristics (TA =
−−−−10 to +70 °°°°C, VCC = 2.7 to 3.6 V)
Parameter
Symbol
Test condition
VCC = 3.0 V
± 0.3 V
VCC = 3.3 V
± 0.3 V
Unit
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
Address access time
tACC
TSOP (I)
100
90
ns
SOP
120
100
Page access time
tPAC
25
25
ns
Address skew time
tSKEW
Note
10
10
ns
Chip enable access time
tCE
TSOP (I)
100
90
ns
SOP
120
100
Output enable access time
tOE
25
25
ns
Output hold time
tOH
00
ns
Output disable time
tDF
0
25
0
25
ns
WORD, /BYTE access time
tWB
TSOP (I)
100
90
ns
SOP
120
100
Note tSKEW indicates the following three types of time depending on the condition.
1) When switching /CE from high level to low level, tSKEW is the time from the /CE low level input point until the
next address is determined.
2) When switching /CE from low level to high level, tSKEW is the time from the address change start point to the
/CE high level input point.
3) When /CE is fixed to low level, tSKEW is the time from the address change start point until the next address is
determined.
Since specs are defined for tSKEW only when /CE is active, tSKEW is not subject to limitations when /CE is
switched from high level to low level following address determination, or when the address is changed after
/CE is switched from low level to high level.
Remark tDF is the time from inactivation of Chip Enable input (/CE) or Output Enable input (/OE or OE) to
high impedance state output.
AC Test Conditions
Input waveform (Rise / Fall Time
≤≤≤≤ 5 ns)
Output waveform
Output load
1 TTL + 100 pF


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