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SN65LV1023A Datasheet(PDF) 6 Page - Texas Instruments |
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SN65LV1023A Datasheet(HTML) 6 Page - Texas Instruments |
6 / 22 page SN65LV1023A/SN65LV1224A 10-MHz TO 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS570A – JUNE 2003 – REVISED JUNE 2003 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions serializer PIN NAME DESCRIPTION 18, 20, 23, 25 AGND Analog circuit ground (PLL and analog circuits) 17, 26 AVCC Analog circuit power supply (PLL and analog circuits) 19 DEN LVTTL logic input. Low puts the LVDS serial output into the high-impedance state. High enables serial data output. 15, 16 DGND Digital circuit ground 3 – 12 DIN0 – DIN9 Parallel LVTTL data inputs 21 DO– Inverting LVDS differential output 22 DO+ Noninverting LVDS differential output 27, 28 DVCC Digital circuit power supply 24 PWRDN LVTTL logic input. Asserting this pin low turns off the PLL and places the outputs into the high-impedance state, putting the device into a low-power mode. 1, 2 SYNC1, SYNC2 LVTTL logic inputs SYNC1 and SYNC2 are ORed together. When at least one of the two pins is asserted high for 6 cycles of TCLK, the serializer initiates transmission of a minimum 1026 SYNC patterns. If after completion of the transmission of 1026 patterns SYNC continues to be asserted, then the transmission continues until SYNC is driven low and if the time SYNC holds > 6 cycles, another 1026 SYNC pattern tranmission initiates. 13 TCLK_R/F LVTTL logic input. Low selects a TCLK falling-edge data strobe; high selects a TCLK rising-edge data strobe. 14 TCLK LVTTL-level reference clock input. The SN65LV1023A accepts a 10-MHz to 66-MHz clock. TCLK strobes parallel data into the input latch and provides a reference frequency to the PLL. deserializer PIN NAME DESCRIPTION 1, 12, 13 AGND Analog circuit ground (PLL and analog circuits) 4, 11 AVCC Analog circuit power supply (PLL and analog circuits) 14, 20, 22 DGND Digital circuit ground 21, 23 DVCC Digital circuit power supply 10 LOCK LVTTL level output. LOCK goes low when the deserializer PLL locks onto the embedded clock edge. 7 PWRDN LVTTL logic input. Asserting this pin low turns off the PLL and places outputs into a high-impedance state, putting the device into a low-power mode. 2 RCLK_R/F LVTTL logic input. Low selects an RCLK falling-edge data strobe; high selects an RCLK rising-edge data strobe. 9 RCLK LVTTL level output recovered clock. Use RCLK to strobe ROUTx. 3 REFCLK LVTTL logic input. Use this pin to supply a REFCLK signal for the internal PLL frequency. 8 REN LVTTL logic input. Low places ROUT0–ROUT9 and RCLK in the high-impedance state. 5 RI+ Serial data input. Noninverting LVDS differential input 6 RI– Serial data input. Inverting LVDS differential input 15 – 19, 24 – 28 ROUT0–ROUT9 Parallel LVTTL data outputs |
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