Philips Semiconductors

PUCC3801

Current-mode PWM controller

Product data

Rev. 01 — 10 September 2001

6 of 16

9397 750 08419

© Koninklijke Philips Electronics N.V. 2001. All rights reserved.

increases to typically 1.2 mA. The device starts normal operation and output pulses

are produced.

output of the over-voltage latch goes HIGH.

exceeds 15 mA.

7.2.2

Controller section

output latch, and a 100 kHz voltage ramp to the PWM circuit. The frequency is

modulated by approximately 20% by a Pseudo Random Binary Sequence (PRBS)

that repeats every 15 cycles. This spreads the electromagnetic interference produced

by the power supply over a narrow band of frequencies centered on 100 kHz. This

reduces the amplitude of the harmonics in the interference spectrum.

control the output duty cycle. It contains an operational transconductance amplifier

(ERRAMP), that can be externally compensated at the COMP pin. The reference

input of ERRAMP is connected to a 2.5 V reference voltage. The FB input is internally

The output of the error amplifier is connected to the PWM section by a voltage divider

with a gain of 0.4 and an output impedance of 100 k

Ω.

low-pass filter, summing amplifier, a high-speed comparator and logic. This section

sums the analog ramp from the oscillator with the voltage on the CSNS pin. This

signal is fed to a comparator that triggers on the falling edge of the PWM clock signal.

This provides line compensation and load regulation. The internal slope

compensation function removes the need for external components to generate a

ramp signal that is added to the current sense signal.

A fast over-current path is provided from CSNS to OUT with a typical propagation

delay of 170 ns.

driving the gate of a large power FET. Typical rise and fall times are 160 ns and

150 ns respectively into a 2 nF load.