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PUCC3801P Datasheet(PDF) 6 Page - NXP Semiconductors |
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PUCC3801P Datasheet(HTML) 6 Page - NXP Semiconductors |
6 / 16 page Philips Semiconductors PUCC3801 Current-mode PWM controller Product data Rev. 01 — 10 September 2001 6 of 16 9397 750 08419 © Koninklijke Philips Electronics N.V. 2001. All rights reserved. When VDD rises above 10 V, VREG rises to 6 V and the operating supply current increases to typically 1.2 mA. The device starts normal operation and output pulses are produced. The over-voltage trip sequence is initiated if VDD rises above 14 V. When this happens, the output pulses are disabled, VREG is reduced gradually to 3 V, and the output of the over-voltage latch goes HIGH. The device remains in the over-voltage lockout mode until VDD falls below 5 V. Input voltage clamp: VDD is clamped to a maximum of 16.5 V. The size of the external resistor must be sufficient to ensure that the current into the VDD pin never exceeds 15 mA. 7.2.2 Controller section Oscillator: The internal oscillator generates a 75% duty cycle digital clock to the output latch, and a 100 kHz voltage ramp to the PWM circuit. The frequency is modulated by approximately 20% by a Pseudo Random Binary Sequence (PRBS) that repeats every 15 cycles. This spreads the electromagnetic interference produced by the power supply over a narrow band of frequencies centered on 100 kHz. This reduces the amplitude of the harmonics in the interference spectrum. Error amplifier: This section senses one of the various feedback methods used to control the output duty cycle. It contains an operational transconductance amplifier (ERRAMP), that can be externally compensated at the COMP pin. The reference input of ERRAMP is connected to a 2.5 V reference voltage. The FB input is internally connected to a voltage divider from VDD. If the FB pin is not connected, the device will tend to regulate VDD to 12 V. The output of the error amplifier is connected to the PWM section by a voltage divider with a gain of 0.4 and an output impedance of 100 k Ω. PWM: The PWM section includes a current sense input from the CSNS pin, a low-pass filter, summing amplifier, a high-speed comparator and logic. This section sums the analog ramp from the oscillator with the voltage on the CSNS pin. This signal is fed to a comparator that triggers on the falling edge of the PWM clock signal. This provides line compensation and load regulation. The internal slope compensation function removes the need for external components to generate a ramp signal that is added to the current sense signal. A fast over-current path is provided from CSNS to OUT with a typical propagation delay of 170 ns. Output driver: This section is a high-speed, high-current output stage capable of driving the gate of a large power FET. Typical rise and fall times are 160 ns and 150 ns respectively into a 2 nF load. |
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