DDR SDRAM

DDR SDRAM 256Mb D-die (x8, x16)

Rev. 1.1 Feb. 2003

DDR SDRAM Spec Items & Test Conditions

Conditions

Symbol

Conditions

Symbol

Operating current - One bank Active-Precharge;

tRC=tRCmin; tCK=5ns for DDR400; DQ,DM and DQS inputs changing once per clock cycle;

address and control inputs changing once every two clock cycles; CS = high between valid commands.

IDD0

Operating current - One bank operation ; One bank open, BL=4, Reads

- Refer to the following page for detailed test condition; CS = high between valid commands.

IDD1

Percharge power-down standby current; All banks idle; power - down mode; CKE = <VIL(max); tCK=5ns for

DDR400; Vin = Vref for DQ,DQS and DM.

IDD2P

Precharge Floating standby current; CS# > =VIH(min);All banks idle; CKE > = VIH(min); tCK=5ns for DDR400;

Address and other control inputs changing once per clock cycle; Vin = Vref for DQ,DQS and DM

IDD2F

Precharge Quiet standby current; CS# > = VIH(min); All banks idle;

CKE > = VIH(min); tCK=5ns for DDR400; Address and other control inputs stable at >= VIH(min) or =<VIL(max);

Vin = Vref for DQ ,DQS and DM

IDD2Q

Active power - down standby current ; one bank active; power-down mode; CKE=< VIL (max); tCK=5ns

DDR400; Vin = Vref for DQ,DQS and DM

IDD3P

Active standby current; CS# >= VIH(min); CKE>=VIH(min);

one bank active; active - precharge; tRC=tRASmax; tCK=5ns for DDR400; DQ, DQS and DM inputs changing twice

per clock cycle; address and other control inputs changing once per clock cycle

IDD3N

Operating current - burst read; Burst length = 2; reads; continguous burst; One bank active; address and control

inputs changing once per clock cycle; CL=3 at 5ns for DDR400; 50% of data changing on every transfer; lout = 0 m

A

IDD4R

Operating current - burst write; Burst length = 2; writes; continuous burst;

One bank active address and control inputs changing once per clock cycle; CL=3 at tCK=5ns for DDR400; DQ, DM

and DQS inputs changing twice per clock cycle, 50% of input data changing at every transfer

IDD4W

Auto refresh current; tRC = tRFC(min) - 14*tCK for DDR400 at tCK=5ns;

IDD5

Self refresh current; CKE =< 0.2V; External clock on; tCK = 5ns for DDR400.

IDD6

Input/Output Capacitance

Parameter

Symbol

Min

Max

Delta

Unit

Note

Input capacitance

(A0 ~ A12, BA0 ~ BA1, CKE, CS, RAS,CAS, WE)

CIN1

2

3

0.5

pF

4

Input capacitance( CK, CK )CIN2

2

3

0.25

pF

4

Data & DQS input/output capacitance

COUT

4

5

0.5

pF

1,2,3,4

Input capacitance(DM for 8, UDM/LDM for x16)

CIN3

4

5

pF

1,2,3,4

1.These values are guaranteed by design and are tested on a sample basis only.

2. Although DM is an input -only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins.

This is required to match signal propagation times of DQ, DQS, and DM in the system.

3. Unused pins are tied to ground.

4. This parameteer is sampled. VDDQ = +2.6V +0.1V, VDD = +2.6V +0.1V, f=100MHz, tA=25

°C, Vout(dc) =

VDDQ/2, Vout(peak to peak) = 0.2V. DM inputs are grouped with I/O pins - reflecting the fact that they are matched in loading

(to facilitate trace matching at the board level).

Note :