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82801FB Datasheet(PDF) 7 Page - Intel Corporation |
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82801FB Datasheet(HTML) 7 Page - Intel Corporation |
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7 / 786 page  Intel® I/O Controller Hub 6 (ICH6) Family Datasheet 7 Contents 5.14.4 SMI#/SCI Generation........................................................................................... 153 5.14.4.1 PCI Express* SCI................................................................................. 155 5.14.4.2 PCI Express* Hot-Plug......................................................................... 155 5.14.5 Dynamic Processor Clock Control ....................................................................... 156 5.14.5.1 Transition Rules among S0/Cx and Throttling States .......................... 157 5.14.5.2 Deferred C3/C4 (Mobile Only) ............................................................. 157 5.14.5.3 POPUP (Auto C3/C4 to C2) (Mobile Only) .......................................... 158 5.14.5.4 POPDOWN (Auto C2 to C3/C4) (Mobile Only) .................................... 158 5.14.6 Dynamic PCI Clock Control (Mobile Only) ........................................................... 158 5.14.6.1 Conditions for Checking the PCI Clock ................................................ 158 5.14.6.2 Conditions for Maintaining the PCI Clock ............................................ 159 5.14.6.3 Conditions for Stopping the PCI Clock................................................. 159 5.14.6.4 Conditions for Re-Starting the PCI Clock............................................. 159 5.14.6.5 LPC Devices and CLKRUN# ...............................................................159 5.14.7 Sleep States ........................................................................................................ 160 5.14.7.1 Sleep State Overview .......................................................................... 160 5.14.7.2 Initiating Sleep State ............................................................................ 160 5.14.7.3 Exiting Sleep States ............................................................................. 160 5.14.7.4 PCI Express* WAKE# Signal and PME Event Message .....................162 5.14.7.5 Sx-G3-Sx, Handling Power Failures .................................................... 162 5.14.8 Thermal Management.......................................................................................... 163 5.14.8.1 THRM# Signal...................................................................................... 163 5.14.8.2 Processor Initiated Passive Cooling .................................................... 163 5.14.8.3 THRM# Override Software Bit ............................................................. 163 5.14.8.4 Active Cooling ...................................................................................... 163 5.14.9 Event Input Signals and Their Usage .................................................................. 164 5.14.9.1 PWRBTN# (Power Button) .................................................................. 164 5.14.9.2 RI# (Ring Indicator) .............................................................................. 165 5.14.9.3 PME# (PCI Power Management Event) .............................................. 165 5.14.9.4 SYS_RESET# Signal ........................................................................... 165 5.14.9.5 THRMTRIP# Signal ............................................................................. 166 5.14.9.6 BMBUSY# (Mobile Only) ..................................................................... 166 5.14.10 ALT Access Mode................................................................................................ 167 5.14.10.1 Write Only Registers with Read Paths in ALT Access Mode ............... 168 5.14.10.2 PIC Reserved Bits................................................................................ 169 5.14.10.3 Read Only Registers with Write Paths in ALT Access Mode ............... 170 5.14.11 System Power Supplies, Planes, and Signals ..................................................... 170 5.14.11.1 Power Plane Control with SLP_S3#, SLP_S4# and SLP_S5# ............ 170 5.14.11.2 SLP_S4# and Suspend-To-RAM Sequencing ..................................... 171 5.14.11.3 PWROK Signal .................................................................................... 171 5.14.11.4 CPUPWRGD Signal............................................................................. 171 5.14.11.5 VRMPWRGD Signal ............................................................................ 171 5.14.11.6 BATLOW# (Battery Low) (Mobile Only) ............................................... 171 5.14.11.7 Controlling Leakage and Power Consumption During Low-Power States .................................................................... 172 5.14.12 Clock Generators ................................................................................................. 172 5.14.12.1 Clock Control Signals from Intel® ICH6 to Clock Synthesizer (Mobile Only) .................................................................... 173 5.14.13 Legacy Power Management Theory of Operation ............................................... 173 5.14.13.1 APM Power Management (Desktop Only) ........................................... 173 5.14.13.2 Mobile APM Power Management (Mobile Only) .................................. 173 5.15 System Management (D31:F0)......................................................................................... 174 5.15.1 Theory of Operation ............................................................................................. 174 |
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