CY28325-3
Document #: 38-07590 Rev. *.*
Page 7 of 19
Data Byte Configuration Map
Data Byte 0
Bit
Pin#
Name
Description
Power-on
Default
7
–
Reserved
Reserved
0
6
–
SEL2
SW Frequency selection bits. Refer to Frequency Selection Table
0
5
–
SEL1
SW Frequency selection bits. Refer to Frequency Selection Table
0
4
–
SEL0
SW Frequency selection bits. Refer to Frequency Selection Table
0
3
–
FS_Override
0 = Select operating frequency by FS[4:0] input pins
1 = Select operating frequency by SEL[4:0] settings
0
2
–
SEL4
SW Frequency selection bits. Refer to Frequency Selection Table
0
1
–
SEL3
SW Frequency selection bits. Refer to Frequency Selection Table
0
0
–
Reserved
Reserved
0
Data Byte 1
Bit
Pin#
Name
Description
Power-on
Default
7
–
Reserved
Reserved
0
6
–
Spread Select2
“000” = OFF
“001” = Reserved
“010” = Reserved
‘011” = Reserved
“100“ = ± 0.25%
“101“ = – 0.5%
“110“= ±0.5%
“111“ = ±0.38%
0
5
–
Spread Select1
0
4
–
Spread Select0
0
3
42, 41
CPUT_CS, CPUC_CS (Active/Inactive)
1
2
35, 34
CPUT_1, CPUC_1
(Active/Inactive)
1
1
40, 39
CPUT_0, CPUC_0
(Active/Inactive)
1
0
–
CPU_CS_F STOP
Control
1 = CPUT_CS_F and CPUC_CS_F are Free-running outputs
0 = CPUT_CS_F and CPUC_CS_F will be disabled when
CPU_STOP# is active
1
Data Byte 2
Bit
Pin#
Name
Pin Description
Power-on
Default
7
21
PCI8
1 = Enabled, 0 = Disabled
1
6
19
PCI7
1 = Enabled, 0 = Disabled
1
5
18
PCI6
1 = Enabled, 0 = Disabled
1
4
17
PCI5
1 = Enabled, 0 = Disabled
1
3
15
PCI4
1 = Enabled, 0 = Disabled
1
2
14
PCI3
1 = Enabled, 0 = Disabled
1
1
12
PCI2
1 = Enabled, 0 = Disabled
1
0
11
PCI1
1 = Enabled, 0 = Disabled
1
Data Byte 3
Bit
Pin#
Name
Pin Description
Power-on
Default
7
–
Reserved
Reserved
0
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