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CY28325-3
Document #: 38-07590 Rev. *.*
Page 3 of 19
VTT_PWRGD#
33
I
Power-good from Voltage Regulator Module (VRM): 3.3V LVTTL input.
VTT_PWRGD# is a level sensitive strobe used to determine when FS0:4
and MULTSEL inputs are valid and OK to be sampled (Active LOW). Once
VTT_PWRGD# is sampled LOW, the status of this input will be ignored.
VDD_CPU_CS,
VDD_APIC
43, 48
P
2.5V Power Connection: Power supply for CPU_CS outputs buffers and
APIC output buffers. Connect to 2.5V.
VDD_REF,
VDD_48MHz,
VDD _PCI,
VDD_AGP,
VDD_CPU
2, 6, 16, 24, 38
P
3.3V Power Connection: Power supply for CPU outputs buffers, 3V66
output buffers, PCI output buffers, reference output buffers and 48-MHz
output buffers. Connect to 3.3V.
GND_REF
GND_48MHz,
GND_PCI,
GND_AGP,
GND_CPU,
GND_APIC
3, 9, 13, 20, 25,
36, 44, 47
G
Ground Connection: Connect all ground pins to the common system
ground plane.
Table 1. Frequency Selection Table
Input Conditions
Output Frequency
PLL Gear
Constants
(G)
FS4
FS3
FS2
FS1
FS0
CPU
AGP
PCI
APIC
SEL4
SEL3
SEL2
SEL1
SEL0
0
0
0
0
0
102.0
68.0
34.0
17.0
48.00741
0
0
0
0
1
105.0
70.0
35.0
17.5
48.00741
0
0
0
1
0
108.0
72.0
36.0
18.0
48.00741
0
0
0
1
1
111.0
74.0
37.0
18.5
48.00741
0
0
1
0
0
114.0
76.0
38.0
19.0
48.00741
0
0
1
0
1
117.0
78.0
39.0
19.5
48.00741
0
0
1
1
0
120.0
80.0
40.0
20.0
48.00741
0
0
1
1
1
123.0
82.0
41.0
20.5
48.00741
0
1
0
0
0
126.0
63.0
31.5
18.0
48.00741
0
1
0
0
1
130.0
65.0
32.5
18.5
48.00741
0
1
0
1
0
136.0
68.0
34.0
17.0
48.00741
0
1
0
1
1
140.0
70.0
35.0
17.5
48.00741
0
1
1
0
0
144.0
72.0
36.0
18.0
48.00741
0
1
1
0
1
148.0
74.0
37.0
18.5
48.00741
0
1
1
1
0
152.0
76.0
38.0
19.0
48.00741
0
1
1
1
1
156.0
78.0
39.0
19.5
48.00741
1
0
0
0
0
160.0
80.0
40.0
20.0
48.00741
1
0
0
0
1
164.0
82.0
41.0
20.5
48.00741
1
0
0
1
0
166.6
66.6
33.3
16.7
48.00741
1
0
0
1
1
170.0
68.0
34.0
17.0
48.00741
1
0
1
0
0
175.0
70.0
35.0
17.5
48.00741
1
0
1
0
1
180.0
72.0
36.0
18.0
48.00741
Pin Definitions (continued)
Pin Name
No.
Type
Description
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